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AdamI75AdamI75
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Merge branch 'devel' of https://github.com/ska-sa/mlib_devel into devel
2 parents 3387e3c + 878f537 commit 45d7b27

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6 files changed

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-4
lines changed

6 files changed

+302
-4
lines changed

‎jasper_library/platforms/red_pitaya_10.yaml‎

Lines changed: 123 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -120,7 +120,129 @@ pins:
120120
DAC_IQRESET:
121121
iostd: LVCMOS33
122122
loc: N15
123-
123+
FIXED_IO_ddr_vrp:
124+
iostd: SSTL15_T_DCI
125+
loc: H5
126+
FIXED_IO_ddr_vrn:
127+
iostd: SSTL15_T_DCI
128+
loc: G5
129+
DDR_we_n:
130+
iostd: SSTL15
131+
loc: M5
132+
DDR_RAS_n:
133+
iostd: SSTL15
134+
loc: P4
135+
DDR_ODT:
136+
iostd: SSTL15
137+
loc: N5
138+
DDR_reset_n:
139+
iostd: SSTL15
140+
loc: B4
141+
DDR_DQS_p:
142+
iostd: DIFF_SSTL15_T_DCI
143+
loc:
144+
- C2
145+
- G2
146+
- R2
147+
- W5
148+
DDR_DQS_n:
149+
iostd: DIFF_SSTL15_T_DCI
150+
loc:
151+
- B2
152+
- F2
153+
- T2
154+
- W4
155+
DDR_DQ:
156+
iostd: SSTL15_T_DCI
157+
loc:
158+
- C3
159+
- B3
160+
- A2
161+
- A4
162+
- D3
163+
- D1
164+
- C1
165+
- E1
166+
- E2
167+
- E3
168+
- G3
169+
- H3
170+
- J3
171+
- H2
172+
- H1
173+
- J1
174+
- P1
175+
- P3
176+
- R3
177+
- R1
178+
- T4
179+
- U4
180+
- U2
181+
- U3
182+
- V1
183+
- Y3
184+
- W1
185+
- Y4
186+
- Y2
187+
- W3
188+
- V2
189+
- V3
190+
DDR_DM:
191+
iostd: DIFF_SSTL15_T_DCI
192+
loc:
193+
- A1
194+
- F1
195+
- T1
196+
- Y1
197+
DDR_CS_n:
198+
iostd: SSTL15
199+
loc: N1
200+
DDR_CKE:
201+
iostd: SSTL15
202+
loc: N3
203+
DDR_Ck_p:
204+
iostd: SSTL15
205+
loc: L2
206+
DDR_Ck_n:
207+
iostd: SSTL15
208+
loc: M2
209+
DDR_CAS_n:
210+
iostd: SSTL15
211+
loc: P5
212+
DDR_ba:
213+
iostd: DIFF_SSTL15
214+
loc:
215+
- L5
216+
- R4
217+
- J5
218+
DDR_Addr:
219+
iostd: SSTL15
220+
loc:
221+
- N2
222+
- K2
223+
- M3
224+
- K3
225+
- M4
226+
- L1
227+
- L4
228+
- K4
229+
- K1
230+
- J4
231+
- F5
232+
- G4
233+
- E4
234+
- D4
235+
- F4
236+
FIXED_IO_ps_porb:
237+
iostd: LVCMOS33
238+
loc: C7
239+
FIXED_IO_ps_srstb:
240+
iostd: LVCMOS33
241+
loc: B10
242+
FIXED_IO_ps_clk:
243+
iostd: LVCMOS33
244+
loc: E7
245+
124246

125247

126248

‎jasper_library/platforms/red_pitaya_14.yaml‎

Lines changed: 131 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -138,6 +138,137 @@ pins:
138138
DAC_IQRESET:
139139
iostd: LVCMOS33
140140
loc: N15
141+
FIXED_IO_ddr_vrp:
142+
iostd: SSTL15_T_DCI
143+
loc: H5
144+
FIXED_IO_ddr_vrn:
145+
iostd: SSTL15_T_DCI
146+
loc: G5
147+
DDR_we_n:
148+
iostd: SSTL15
149+
loc: M5
150+
DDR_RAS_n:
151+
iostd: SSTL15
152+
loc: P4
153+
DDR_ODT:
154+
iostd: SSTL15
155+
loc: N5
156+
DDR_reset_n:
157+
iostd: SSTL15
158+
loc: B4
159+
DDR_DQS_p:
160+
iostd: DIFF_SSTL15_T_DCI
161+
loc:
162+
- C2
163+
- G2
164+
- R2
165+
- W5
166+
DDR_DQS_n:
167+
iostd: DIFF_SSTL15_T_DCI
168+
loc:
169+
- B2
170+
- F2
171+
- T2
172+
- W4
173+
DDR_DQ:
174+
iostd: SSTL15_T_DCI
175+
loc:
176+
- C3
177+
- B3
178+
- A2
179+
- A4
180+
- D3
181+
- D1
182+
- C1
183+
- E1
184+
- E2
185+
- E3
186+
- G3
187+
- H3
188+
- J3
189+
- H2
190+
- H1
191+
- J1
192+
- P1
193+
- P3
194+
- R3
195+
- R1
196+
- T4
197+
- U4
198+
- U2
199+
- U3
200+
- V1
201+
- Y3
202+
- W1
203+
- Y4
204+
- Y2
205+
- W3
206+
- V2
207+
- V3
208+
DDR_DM:
209+
iostd: DIFF_SSTL15_T_DCI
210+
loc:
211+
- A1
212+
- F1
213+
- T1
214+
- Y1
215+
DDR_CS_n:
216+
iostd: SSTL15
217+
loc: N1
218+
DDR_CKE:
219+
iostd: SSTL15
220+
loc: N3
221+
DDR_Ck_p:
222+
iostd: SSTL15
223+
loc: L2
224+
DDR_Ck_n:
225+
iostd: SSTL15
226+
loc: M2
227+
DDR_CAS_n:
228+
iostd: SSTL15
229+
loc: P5
230+
DDR_ba:
231+
iostd: DIFF_SSTL15
232+
loc:
233+
- L5
234+
- R4
235+
- J5
236+
DDR_Addr:
237+
iostd: SSTL15
238+
loc:
239+
- N2
240+
- K2
241+
- M3
242+
- K3
243+
- M4
244+
- L1
245+
- L4
246+
- K4
247+
- K1
248+
- J4
249+
- F5
250+
- G4
251+
- E4
252+
- D4
253+
- F4
254+
FIXED_IO_ps_porb:
255+
iostd: LVCMOS33
256+
loc: C7
257+
FIXED_IO_ps_srstb:
258+
iostd: LVCMOS33
259+
loc: B10
260+
FIXED_IO_ps_clk:
261+
iostd: LVCMOS33
262+
loc: E7
263+
264+
265+
266+
267+
268+
269+
270+
271+
141272

142273

143274

‎jasper_library/toolflow.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2043,7 +2043,7 @@ def gen_add_compile_dir_source_tcl_cmds(self):
20432043
c = obj.add_build_dir_source()
20442044
for d in c:
20452045
#self.add_source('%s/%s' %(self.compile_dir, d['files']), self.plat)
2046-
self.add_tcl_cmd('add_files %s/%s' %(self.compile_dir, d['files']), stage='pre_synth')
2046+
self.add_tcl_cmd('import_files %s/%s' %(self.compile_dir, d['files']), stage='pre_synth')
20472047
#if d['library'] != '':
20482048
# add the source to a library if the library key exists
20492049
# self.add_tcl_cmd('set_property library %s [get_files {%s/%s%s}]' %(d['library'], self.compile_dir, d['files'], '*' if d['files'][-1]=='/' else ''), stage='pre_synth')

‎jasper_library/yellow_blocks/axi4lite_interconnect.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ def gen_tcl_cmds(self):
7878
print('=====================')
7979
tcl_cmds = {}
8080
tcl_cmds['pre_synth'] = []
81-
tcl_cmds['pre_synth'] += ['add_files {%s/axi4_lite/axi4lite_slave_logic.vhd %s/axi4_lite/axi4lite_pkg.vhd}' %(self.hdl_root, self.hdl_root)]
81+
tcl_cmds['pre_synth'] += ['import_files {%s/axi4_lite/axi4lite_slave_logic.vhd %s/axi4_lite/axi4lite_pkg.vhd}' %(self.hdl_root, self.hdl_root)]
8282
tcl_cmds['pre_synth'] += ['update_compile_order -fileset sources_1']
8383
return tcl_cmds
8484

‎jasper_library/yellow_blocks/red_pitaya.py‎

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,28 @@ def modify_top(self,top):
2626
inst.add_port('axil_rst', 'axil_rst')
2727
inst.add_port('axil_rst_n', 'axil_rst_n')
2828

29+
inst.add_port('FIXED_IO_ddr_vrp', 'FIXED_IO_ddr_vrp', dir='inout', parent_port=True)
30+
inst.add_port('FIXED_IO_ddr_vrn', 'FIXED_IO_ddr_vrn', dir='inout', parent_port=True)
31+
inst.add_port('DDR_we_n', 'DDR_we_n', dir='inout', parent_port=True)
32+
inst.add_port('DDR_RAS_n', 'DDR_RAS_n', dir='inout', width=1, parent_port=True)
33+
inst.add_port('DDR_ODT', 'DDR_ODT', dir='inout', parent_port=True)
34+
inst.add_port('DDR_reset_n', 'DDR_reset_n', dir='inout', parent_port=True)
35+
inst.add_port('DDR_DQS_p', 'DDR_DQS_p', dir='inout', width=4, parent_port=True)
36+
inst.add_port('DDR_DQS_n', 'DDR_DQS_n', dir='inout', width=4, parent_port=True)
37+
inst.add_port('DDR_DQ', 'DDR_DQ', dir='inout', width=32, parent_port=True)
38+
inst.add_port('DDR_DM', 'DDR_DM', dir='inout', width=4, parent_port=True)
39+
inst.add_port('DDR_CS_n', 'DDR_CS_n', dir='inout', parent_port=True)
40+
inst.add_port('DDR_CKE', 'DDR_CKE', dir='inout', parent_port=True)
41+
inst.add_port('DDR_Ck_p', 'DDR_Ck_p', dir='inout', parent_port=True)
42+
inst.add_port('DDR_Ck_n', 'DDR_Ck_n', dir='inout', parent_port=True)
43+
inst.add_port('DDR_CAS_n', 'DDR_CAS_n', dir='inout', parent_port=True)
44+
inst.add_port('DDR_ba', 'DDR_ba', dir='inout', width=3, parent_port=True)
45+
inst.add_port('DDR_Addr', 'DDR_Addr', dir='inout', width=15, parent_port=True)
46+
47+
inst.add_port('FIXED_IO_ps_porb', 'FIXED_IO_ps_porb', dir='inout', parent_port=True)
48+
inst.add_port('FIXED_IO_ps_srstb', 'FIXED_IO_ps_srstb', dir='inout', parent_port=True)
49+
inst.add_port('FIXED_IO_ps_clk', 'FIXED_IO_ps_clk', dir='inout', parent_port=True)
50+
2951
inst.add_port('M_AXI_araddr', 'M_AXI_araddr', width=32)
3052
inst.add_port('M_AXI_arprot', 'M_AXI_arprot', width=3)
3153
inst.add_port('M_AXI_arready', 'M_AXI_arready')
@@ -76,6 +98,29 @@ def gen_children(self):
7698

7799
def gen_constraints(self):
78100
cons = []
101+
102+
cons.append(PortConstraint('FIXED_IO_ddr_vrp', 'FIXED_IO_ddr_vrp'))
103+
cons.append(PortConstraint('FIXED_IO_ddr_vrn', 'FIXED_IO_ddr_vrn'))
104+
cons.append(PortConstraint('DDR_we_n', 'DDR_we_n'))
105+
cons.append(PortConstraint('DDR_RAS_n', 'DDR_RAS_n'))
106+
cons.append(PortConstraint('DDR_ODT', 'DDR_ODT'))
107+
cons.append(PortConstraint('DDR_reset_n', 'DDR_reset_n'))
108+
cons.append(PortConstraint('DDR_DQS_p', 'DDR_DQS_p', port_index=list(range(4)), iogroup_index=list(range(4))))
109+
cons.append(PortConstraint('DDR_DQS_n', 'DDR_DQS_n', port_index=list(range(4)), iogroup_index=list(range(4))))
110+
cons.append(PortConstraint('DDR_DQ', 'DDR_DQ', port_index=list(range(32)), iogroup_index=list(range(32))))
111+
cons.append(PortConstraint('DDR_DM', 'DDR_DM', port_index=list(range(4)), iogroup_index=list(range(4))))
112+
cons.append(PortConstraint('DDR_CS_n', 'DDR_CS_n'))
113+
cons.append(PortConstraint('DDR_CKE', 'DDR_CKE'))
114+
cons.append(PortConstraint('DDR_Ck_p', 'DDR_Ck_p'))
115+
cons.append(PortConstraint('DDR_Ck_n', 'DDR_Ck_n'))
116+
cons.append(PortConstraint('DDR_CAS_n', 'DDR_CAS_n'))
117+
cons.append(PortConstraint('DDR_ba', 'DDR_ba', port_index=list(range(3)), iogroup_index=list(range(3))))
118+
cons.append(PortConstraint('DDR_Addr', 'DDR_Addr', port_index=list(range(15)), iogroup_index=list(range(15))))
119+
120+
cons.append(PortConstraint('FIXED_IO_ps_porb', 'FIXED_IO_ps_porb'))
121+
cons.append(PortConstraint('FIXED_IO_ps_srstb', 'FIXED_IO_ps_srstb'))
122+
cons.append(PortConstraint('FIXED_IO_ps_clk', 'FIXED_IO_ps_clk'))
123+
79124
cons.append(PortConstraint('ADC_CLK_IN_P', 'ADC_CLK_IN_P'))
80125
cons.append(ClockConstraint('ADC_CLK_IN_P','ADC_CLK_IN_P', period=8.0, port_en=True, virtual_en=False, waveform_min=0.0, waveform_max=4.0))
81126
cons.append(ClockGroupConstraint('-of_objects [get_pins red_pitaya_infr_inst/dsp_clk_mmcm_inst/CLKOUT0]', '-of_objects [get_pins red_pitaya_inst/processing_system7_0/inst/PS7_i/FCLKCLK[0]]', 'asynchronous'))

‎requirements.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,4 +4,4 @@ pyaml
44
odict
55
#xml2vhdl requirements
66
lxml
7-
-e git+http://github.com/casper-astro/xml2vhdl#egg=xml2vhdl_ox-0.2.1-py3.5.egg&subdirectory=scripts/python/xml2vhdl-ox
7+
-e git+http://github.com/casper-astro/xml2vhdl#egg=xml2vhdl_ox-0.2.2-py3.5.egg&subdirectory=scripts/python/xml2vhdl-ox

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