Port to Clash 1.4.2

Author: christiaanb

Makefile

@@ -71,7 +71,7 @@ ICO_BF_SOURCES=\
 build/ico_soc_clash.v: $(ICO_RTL_SOURCES) build/stack
 	rtl/clash -irtl/src -iarch/src -outputdir build/clash \
 	          -fclash-inline-limit=50 --verilog rtl/src/RTL/IcoTop.hs
-	cat build/clash/verilog/RTL/ico_soc/*.v > $@
+	cat build/clash/RTL.IcoTop.topEntity/*.v > $@
 
 build/ico.blif: build/ico_soc_clash.v rtl/syn/ico-top.v
 	cd rtl/syn && yosys -q \
@@ -143,7 +143,7 @@ ICE_BF_SOURCES=\
 build/icestick_soc_clash.v: $(ICE_RTL_SOURCES) build/stack
 	rtl/clash -irtl/src -iarch/src -outputdir build/clash \
 	          -fclash-inline-limit=50 --verilog rtl/src/RTL/IcestickTop.hs
-	cat build/clash/verilog/RTL/icestick_soc/*.v > $@
+	cat build/clash/RTL.IcestickTop.topEntity/*.v > $@
 
 build/icestick.blif: build/icestick_soc_clash.v rtl/syn/icestick-top.v
 	cd rtl/syn && yosys -q \

arch/src/CFM/Inst.hs

@@ -15,7 +15,6 @@ module CFM.Inst
   ) where
 
 import Clash.Prelude
-import GHC.Generics
 import Control.DeepSeq (NFData)
 import Test.QuickCheck
 
@@ -69,7 +68,7 @@ data TMux = T         -- ^ 0: Same value as this cycle.
           deriving (Eq, Enum, Bounded, Show)
 
 data Space = MSpace | ISpace
-  deriving (Eq, Show, Enum, Bounded, Generic, ShowX, NFData)
+  deriving (Eq, Show, Enum, Bounded, Generic, ShowX, NFData, NFDataX)
 
 instance BitPack Space where
   type BitSize Space = 1

rtl/src/RTL/Beh.hs

@@ -68,7 +68,7 @@ executeNormally = do
       msRPtr += 1  -- push return stack
       fetch
         <&> osROp . _2 .~ 1
-        <&> osROp . _3 .~ Just (zeroExtend $ pc' ++# low)
+        <&> osROp . _3 .~ Just (zeroExtend $ pc' ++# pack low)
 
     NotLit (ALU rpc t' tn tr nm space rd dd) -> do
       n <- view isDData

rtl/src/RTL/BootROM.hs

@@ -31,7 +31,7 @@ import CFM.Types
 -- monitors the CPU fetch bus, and on the *second* such jump (the first having
 -- activated the boot program at reset), the interposer disables itself and
 -- normal RAM is exposed.
-bootROM :: (HasClockReset d g s, KnownNat a)
+bootROM :: (HiddenClockResetEnable d, KnownNat a)
         => SNat n
           -- ^ Size of the ROM.
         -> FilePath

rtl/src/RTL/Core.hs

@@ -13,14 +13,14 @@ import RTL.Str
 import RTL.CoreInterface
 
 -- | Registered version of the core datapath.
-core :: HasClockReset dom gated synchronous
+core :: HiddenClockResetEnable dom
      => Signal dom IS -> Signal dom OS
 core = mealy datapath def
 
 -- | Combines 'core' with the selected implementation of stacks, and exposes
 -- the local bus interface.
 coreWithStacks
-  :: (HasClockReset dom gated synchronous)
+  :: (HiddenClockResetEnable dom)
   => Signal dom Cell    -- ^ read response from memory
   -> Signal dom Cell    -- ^ read response from I/O
   -> ( Signal dom BusReq
@@ -38,7 +38,7 @@ coreWithStacks mresp ioresp = (mreq, ireq, fetch)
     n = stack "D" $ coreOuts <&> (^. osDOp)
     r = stack "R" $ coreOuts <&> (^. osROp)
 
-stack :: (HasClockReset d g s)
+stack :: (HiddenClockResetEnable d)
       => String -> Signal d (SP, SDelta, Maybe Cell) -> Signal d Cell
 stack name op = readNew (blockRamPow2 (repeat $ errorX name))
                         (op <&> (^. _1) <&> unpack)
@@ -50,7 +50,7 @@ stack name op = readNew (blockRamPow2 (repeat $ errorX name))
 -- | Combines 'coreWithStacks' with a RAM built from the given constructor, and
 -- an I/O bridge, exposing the I/O bus.
 coreWithRAM
-  :: (HasClockReset dom gated synchronous)
+  :: (HiddenClockResetEnable dom)
   => (Signal dom (Maybe (CellAddr, Maybe Cell)) -> Signal dom Cell)
     -- ^ RAM constructor
   -> Signal dom Cell    -- ^ I/O read response, valid when addressed.

rtl/src/RTL/CoreInterface.hs

@@ -8,7 +8,6 @@
 module RTL.CoreInterface where
 
 import Clash.Prelude hiding (cycle)
-import GHC.Generics
 
 import Control.DeepSeq (NFData)
 import Control.Lens hiding ((:>))
@@ -24,7 +23,7 @@ data BusState = BusFetch
               | BusData Bool
                 -- ^ The bus was used for something else. The bool flag
                 -- indicates that the bus response should be written to T.
-  deriving (Eq, Show, Generic, ShowX, NFData)
+  deriving (Eq, Show, Generic, ShowX, NFData, NFDataX)
 
 instance Arbitrary BusState where
   arbitrary = oneof [ pure BusFetch
@@ -46,7 +45,7 @@ data MS = MS
   , _msT :: Cell
   , _msBusState :: BusState
   , _msLastSpace :: Space
-  } deriving (Show, Generic, ShowX, NFData)
+  } deriving (Show, Generic, ShowX, NFData, NFDataX)
 makeLenses ''MS
 
 -- At reset, pretend we're in the second phase of a store. We'll ignore the

rtl/src/RTL/GPIO.hs

@@ -1,5 +1,7 @@
 {-# LANGUAGE NoImplicitPrelude #-}
 {-# LANGUAGE DataKinds #-}
+{-# LANGUAGE DeriveAnyClass #-}
+{-# LANGUAGE DeriveGeneric #-}
 {-# LANGUAGE ScopedTypeVariables #-}
 {-# LANGUAGE TypeOperators #-}
 {-# LANGUAGE TypeFamilies #-}
@@ -17,7 +19,7 @@ import CFM.Types
 -- - +4: NAND output pins. 1 bits will clear pins, 0 bits have no effect.
 --
 -- Reading from any address gets the current pin status.
-outport :: (HasClockReset d g s)
+outport :: (HiddenClockResetEnable d)
         => Signal d (Maybe (BitVector 2, Maybe Cell))
         -> ( Signal d Cell
            , Signal d Cell
@@ -41,7 +43,7 @@ outport = moorep outportT repeat id (pure ())
 --
 -- It also produces an interrupt on negative edges of bit 0. The interrupt
 -- condition can be cleared by any write to the port's address space.
-inport :: (KnownNat a, HasClockReset d g s)
+inport :: (KnownNat a, HiddenClockResetEnable d)
        => Signal d Cell
        -> Signal d (Maybe (BitVector a, Maybe Cell))
        -> ( Signal d Cell
@@ -56,7 +58,7 @@ inport = moorep inportT (repeat . \(InportS x _) -> x) (\(InportS _ x) -> x)
           Just (_, Just _) -> False
           -- Otherwise, OR in the negative edge detector.
           _                -> irq || negedge
-        negedge = unpack (lsb reg .&. complement (lsb port))
+        negedge = bitCoerce (lsb reg .&. complement (lsb port))
 
-data InportS = InportS Cell Bool deriving (Show)
+data InportS = InportS Cell Bool deriving (Show, Generic, NFDataX)
 instance Default InportS where def = InportS def False

rtl/src/RTL/IOBus.hs

@@ -75,7 +75,7 @@ topBits = fst . split
 -- Each cycle, the 'ioDecoder' sends its muxing decision as a @BitVector m@
 -- (when an I/O device is selected at all. On the next cycle, the 'responseMux'
 -- selects the corresponding channel out of @2 ^ m@ device response channels.
-responseMux :: forall m t d g s. (KnownNat m, HasClockReset d g s)
+responseMux :: forall m t d. (KnownNat m, HiddenClockResetEnable d)
             => Vec (2 ^ m) (Signal d t)  -- ^ response from each device
             -> Signal d (Maybe (BitVector m)) -- ^ decoder output
             -> Signal d t  -- ^ response to core
@@ -98,7 +98,7 @@ partialDecode = fmap truncateAddr
 --
 -- The reset state of the machine is given by 'def' for the state type, for
 -- convenience.
-moorep :: (KnownNat a, HasClockReset dom gated synchronous, Default s)
+moorep :: (KnownNat a, HiddenClockResetEnable dom, Default s, NFDataX s)
        => (s -> (Maybe (BitVector a, Maybe Cell), i) -> s)
         -- ^ State transition function.
        -> (s -> Vec (2^a) Cell)
@@ -129,7 +129,7 @@ moorep ft fr fo = \inp ioreq ->
 --
 -- The reset state of the machine is given by 'def' for the state type, for
 -- convenience.
-mealyp :: (KnownNat a, HasClockReset dom gated synchronous, Default s)
+mealyp :: (KnownNat a, HiddenClockResetEnable dom, Default s, NFDataX s)
        => (s -> (Maybe (BitVector a, Maybe Cell), i) -> (s, o))
         -- ^ State transition and outputs function.
        -> (s -> Vec (2^a) Cell)

rtl/src/RTL/IRQ.hs

@@ -1,5 +1,7 @@
 {-# LANGUAGE NoImplicitPrelude #-}
 {-# LANGUAGE DataKinds #-}
+{-# LANGUAGE DeriveAnyClass #-}
+{-# LANGUAGE DeriveGeneric #-}
 {-# LANGUAGE ScopedTypeVariables #-}
 {-# LANGUAGE TypeOperators #-}
 {-# LANGUAGE ViewPatterns #-}
@@ -28,7 +30,7 @@ vectorMux vf = mux (fromStrobe <$> vf) (pure $ pack $ NotLit $ Call 1)
 -- space. They are disabled when an interrupt occurs. Currently, there is no
 -- way to disable interrupts programatically.
 singleIrqController
-  :: (HasClockReset d g s)
+  :: (HiddenClockResetEnable d)
   => Signal d Bool    -- ^ Interrupt input, active high, level-sensitive.
   -> Signal d Bool    -- ^ CPU fetch signal, active high.
   -> Signal d (Maybe (BitVector 1, Maybe Cell))   -- ^ I/O bus request.
@@ -67,7 +69,7 @@ data SIS = SIS
   , sisEnter :: Bool
     -- ^ Interrupt entry event strobe. Goes high on the cycle when a fetch
     -- is being replaced by a vector.
-  } deriving (Show)
+  } deriving (Show, Generic, NFDataX)
 
 instance Default SIS where def = SIS False False
 
@@ -96,7 +98,7 @@ instance Default SIS where def = SIS False False
 --    interrupt. On writes, zero bits are ignored. Reads as the interrupt
 --    enable mask (the same as IRQSE).
 multiIrqController
-  :: (HasClockReset d g s)
+  :: (HiddenClockResetEnable d)
   => Vec Width (Signal d Bool)
       -- ^ Interrupt inputs, active high, level-sensitive.
   -> Signal d Bool    -- ^ CPU fetch signal, active high.
@@ -123,7 +125,7 @@ multiIrqController irqS fetchS reqS = (vfaS, vfdS, eiS, respS)
               -- Any write to the enable-trigger register enables.
               Just (0, Just _) -> True
               -- The bottom bit of writes @ 1 gets copied into the enable bit.
-              Just (1, Just v) -> unpack $ lsb v
+              Just (1, Just v) -> bitCoerce $ lsb v
               -- Anything else leaves matters unchanged.
               _                -> misEn s
 
@@ -154,7 +156,7 @@ data MIS = MIS
     -- ^ Individual interrupt enable flags.
   , misEnter :: Bool
     -- ^ Vector fetch flag. Set during the cycle where we intercede in fetch.
-  } deriving (Show)
+  } deriving (Show, Generic, NFDataX)
 
 instance Default MIS where
   def = MIS False (repeat False) (repeat False) False

rtl/src/RTL/IcestickTop.hs

@@ -14,7 +14,7 @@ import RTL.GPIO
 import RTL.Core
 import RTL.UART
 
-system :: (HasClockReset dom gated synchronous)
+system :: (HiddenClockResetEnable dom)
        => FilePath
        -> Signal dom Cell
        -> Signal dom Bit  -- UART RX
@@ -36,20 +36,20 @@ system raminit ins urx = (outs, utx)
                               partialDecode ioreq3
     irqs = irq0 :> urxne :> repeat (pure False)
 
-{-# ANN topEntity (defTop { t_name = "icestick_soc"
-                          , t_inputs = [ PortName "clk_core"
-                                       , PortName "reset"
-                                       , PortName "inport"
-                                       , PortName "uart_rx"
-                                       ]
-                          , t_output = PortField ""
-                                       [ PortName "out1"
-                                       , PortName "uart_tx"
-                                       ]
-                          }) #-}
-topEntity :: Clock System 'Source
-          -> Reset System 'Asynchronous
+{-# ANN topEntity (Synthesize { t_name = "icestick_soc"
+                              , t_inputs = [ PortName "clk_core"
+                                           , PortName "reset"
+                                           , PortName "inport"
+                                           , PortName "uart_rx"
+                                           ]
+                              , t_output = PortProduct ""
+                                           [ PortName "out1"
+                                           , PortName "uart_tx"
+                                           ]
+                              }) #-}
+topEntity :: Clock System
+          -> Reset System
           -> Signal System Cell
           -> Signal System Bit
           -> (Signal System Cell, Signal System Bit)
-topEntity c r = withClockReset c r $ system "random-3k5.readmemb"
+topEntity c r = withClockResetEnable c r enableGen $ system "rtl/syn/random-3k5.readmemb"