@@ -2187,6 +2187,7 @@ static void _emitTEXSampleTextureCode(LatteDecompilerShaderContext* shaderContex
2187
2187
}
2188
2188
2189
2189
auto texDim = shaderContext->shader ->textureUnitDim [texInstruction->textureFetch .textureIndex ];
2190
+ bool isCompare = shaderContext->shader ->textureUsesDepthCompare [texInstruction->textureFetch .textureIndex ];
2190
2191
2191
2192
char tempBuffer0[32 ];
2192
2193
char tempBuffer1[32 ];
@@ -2212,6 +2213,7 @@ static void _emitTEXSampleTextureCode(LatteDecompilerShaderContext* shaderContex
2212
2213
}
2213
2214
// texture sampler opcode
2214
2215
uint32 texOpcode = texInstruction->opcode ;
2216
+ // TODO: is this needed?
2215
2217
if (shaderContext->shaderType == LatteConst::ShaderType::Vertex)
2216
2218
{
2217
2219
// vertex shader forces LOD to zero, but certain sampler types don't support textureLod(...) API
@@ -2275,7 +2277,10 @@ static void _emitTEXSampleTextureCode(LatteDecompilerShaderContext* shaderContex
2275
2277
}
2276
2278
else
2277
2279
{
2278
- src->addFmt (" sample(samplr{}, " , texInstruction->textureFetch .textureIndex );
2280
+ src->add (" sample" );
2281
+ if (isCompare)
2282
+ src->add (" _compare" );
2283
+ src->addFmt (" (samplr{}, " , texInstruction->textureFetch .textureIndex );
2279
2284
}
2280
2285
2281
2286
// for textureGather() add shift (todo: depends on rounding mode set in sampler registers?)
@@ -2493,61 +2498,68 @@ static void _emitTEXSampleTextureCode(LatteDecompilerShaderContext* shaderContex
2493
2498
src->addFmt (" ,int3({},{},{})" , texInstruction->textureFetch .offsetX /2 , texInstruction->textureFetch .offsetY /2 , texInstruction->textureFetch .offsetZ /2 );
2494
2499
}
2495
2500
}
2496
- // lod bias
2497
- if ( texOpcode == GPU7_TEX_INST_SAMPLE_C || texOpcode == GPU7_TEX_INST_SAMPLE_C_LZ )
2498
- {
2499
- src->add (" )." );
2500
2501
2501
- if (numWrittenElements > 1 )
2502
- {
2503
- // result is copied into multiple channels
2504
- for (sint32 f = 0 ; f < numWrittenElements; f++)
2505
- {
2506
- cemu_assert_debug (texInstruction->dstSel [f] == 0 ); // only x component is defined
2507
- src->add (" x" );
2508
- }
2509
- }
2510
- else
2511
- {
2512
- src->add (" x" );
2513
- }
2514
- }
2515
- else
2516
- {
2517
- src->add (" )." );
2518
- for (sint32 f = 0 ; f < 4 ; f++)
2519
- {
2520
- if ( texInstruction->dstSel [f] < 4 )
2521
- {
2522
- uint8 elemIndex = texInstruction->dstSel [f];
2523
- if (texOpcode == GPU7_TEX_INST_FETCH4)
2524
- {
2525
- // 's textureGather() and GPU7's FETCH4 instruction have a different order of elements
2526
- // xyzw: top-left, top-right, bottom-right, bottom-left
2527
- // textureGather xyzw
2528
- // fetch4 yzxw
2529
- // translate index from fetch4 to textureGather order
2530
- static uint8 fetchToGather[4 ] =
2531
- {
2532
- 2 , // x -> z
2533
- 0 , // y -> x
2534
- 1 , // z -> y
2535
- 3 , // w -> w
2536
- };
2537
- elemIndex = fetchToGather[elemIndex];
2538
- }
2539
- src->add (resultElemTable[elemIndex]);
2540
- numWrittenElements++;
2541
- }
2542
- else if ( texInstruction->dstSel [f] == 7 )
2543
- {
2544
- // masked and not written
2545
- }
2546
- else
2547
- {
2548
- cemu_assert_unimplemented ();
2549
- }
2550
- }
2502
+ // lod bias (TODO: wht?)
2503
+
2504
+ src->add (" )" );
2505
+ // sample_compare doesn't return a float
2506
+ if (!isCompare)
2507
+ {
2508
+ if ( texOpcode == GPU7_TEX_INST_SAMPLE_C || texOpcode == GPU7_TEX_INST_SAMPLE_C_LZ )
2509
+ {
2510
+ src->add (" ." );
2511
+
2512
+ if (numWrittenElements > 1 )
2513
+ {
2514
+ // result is copied into multiple channels
2515
+ for (sint32 f = 0 ; f < numWrittenElements; f++)
2516
+ {
2517
+ cemu_assert_debug (texInstruction->dstSel [f] == 0 ); // only x component is defined
2518
+ src->add (" x" );
2519
+ }
2520
+ }
2521
+ else
2522
+ {
2523
+ src->add (" x" );
2524
+ }
2525
+ }
2526
+ else
2527
+ {
2528
+ src->add (" ." );
2529
+ for (sint32 f = 0 ; f < 4 ; f++)
2530
+ {
2531
+ if ( texInstruction->dstSel [f] < 4 )
2532
+ {
2533
+ uint8 elemIndex = texInstruction->dstSel [f];
2534
+ if (texOpcode == GPU7_TEX_INST_FETCH4)
2535
+ {
2536
+ // 's textureGather() and GPU7's FETCH4 instruction have a different order of elements
2537
+ // xyzw: top-left, top-right, bottom-right, bottom-left
2538
+ // textureGather xyzw
2539
+ // fetch4 yzxw
2540
+ // translate index from fetch4 to textureGather order
2541
+ static uint8 fetchToGather[4 ] =
2542
+ {
2543
+ 2 , // x -> z
2544
+ 0 , // y -> x
2545
+ 1 , // z -> y
2546
+ 3 , // w -> w
2547
+ };
2548
+ elemIndex = fetchToGather[elemIndex];
2549
+ }
2550
+ src->add (resultElemTable[elemIndex]);
2551
+ numWrittenElements++;
2552
+ }
2553
+ else if ( texInstruction->dstSel [f] == 7 )
2554
+ {
2555
+ // masked and not written
2556
+ }
2557
+ else
2558
+ {
2559
+ cemu_assert_unimplemented ();
2560
+ }
2561
+ }
2562
+ }
2551
2563
}
2552
2564
src->add (" );" );
2553
2565
0 commit comments