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scaprilescaprile
authored
Merge pull request #3290 from cesanta/stm32n6
Add STM32N driver support
2 parents 01902bb + 0d58748 commit 0f83c2a

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4 files changed

+44
-24
lines changed

4 files changed

+44
-24
lines changed

‎mongoose.c‎

Lines changed: 18 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -24272,9 +24272,10 @@ struct mg_tcpip_driver mg_tcpip_driver_stm32f = {
2427224272
#endif
2427324273

2427424274

24275-
#if MG_ENABLE_TCPIP && (MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN)
24275+
#if MG_ENABLE_TCPIP && (MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN || \
24276+
MG_ENABLE_DRIVER_STM32N)
2427624277
// STM32H: vendor modded single-queue Synopsys v4.2
24277-
// MCXNx4x: dual-queue Synopsys v5.2 with no hash table option
24278+
// STM32N, MCXNx4x: dual-queue Synopsys v5.2 with no hash table option
2427824279
// RT1170 ENET_QOS: quad-queue Synopsys v5.1
2427924280
struct synopsys_enet_qos {
2428024281
volatile uint32_t MACCR, MACECR, MACPFR, MACWTR, MACHT0R, MACHT1R,
@@ -24313,17 +24314,20 @@ struct synopsys_enet_qos {
2431324314
0x8000UL))
2431424315
#elif MG_ENABLE_DRIVER_MCXN
2431524316
#define ETH ((struct synopsys_enet_qos *) (uintptr_t) 0x40100000UL)
24317+
#elif MG_ENABLE_DRIVER_STM32N
24318+
#define ETH ((struct synopsys_enet_qos *) (uintptr_t) 0x48036000UL)
2431624319
#endif
2431724320

2431824321
#define ETH_PKT_SIZE 1540 // Max frame size
2431924322
#define ETH_DESC_CNT 4 // Descriptors count
2432024323
#define ETH_DS 4 // Descriptor size (words)
2432124324

24322-
static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS]; // RX descriptors
24323-
static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS]; // TX descriptors
24324-
static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // RX ethernet buffers
24325-
static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // TX ethernet buffers
24326-
static struct mg_tcpip_if *s_ifp; // MIP interface
24325+
#define MG_8BYTE_ALIGNED __attribute__((aligned(8)))
24326+
static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS] MG_8BYTE_ALIGNED;
24327+
static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS] MG_8BYTE_ALIGNED;
24328+
static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_8BYTE_ALIGNED;
24329+
static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_8BYTE_ALIGNED;
24330+
static struct mg_tcpip_if *s_ifp; // MIP interface
2432724331

2432824332
static uint16_t eth_read_phy(uint8_t addr, uint8_t reg) {
2432924333
ETH->MACMDIOAR &= (0xF << 8);
@@ -24374,7 +24378,7 @@ static bool mg_tcpip_driver_stm32h_init(struct mg_tcpip_if *ifp) {
2437424378
ETH->DMASBMR |= MG_BIT(12); // AAL NOTE(scaprile): is this actually needed
2437524379
ETH->MACIER = 0; // Do not enable additional irq sources (reset value)
2437624380
ETH->MACTFCR = MG_BIT(7); // Disable zero-quanta pause
24377-
#if !MG_ENABLE_DRIVER_MCXN
24381+
#if MG_ENABLE_DRIVER_STM32H
2437824382
ETH->MACPFR = MG_BIT(10); // Perfect filtering
2437924383
#endif
2438024384
struct mg_phy phy = {eth_read_phy, eth_write_phy};
@@ -24443,7 +24447,7 @@ static size_t mg_tcpip_driver_stm32h_tx(const void *buf, size_t len,
2444324447
}
2444424448

2444524449
static void mg_tcpip_driver_stm32h_update_hash_table(struct mg_tcpip_if *ifp) {
24446-
#if MG_ENABLE_DRIVER_MCXN
24450+
#if MG_ENABLE_DRIVER_MCXN || MG_ENABLE_DRIVER_STM32N
2444724451
ETH->MACPFR = MG_BIT(4); // Pass Multicast (pass all multicast frames)
2444824452
#else
2444924453
// TODO(): read database, rebuild hash table
@@ -24454,7 +24458,7 @@ static void mg_tcpip_driver_stm32h_update_hash_table(struct mg_tcpip_if *ifp) {
2445424458
ETH->MACA1HR = (uint32_t) mcast_addr[5] << 8 | (uint32_t) mcast_addr[4];
2445524459
ETH->MACA1HR |= MG_BIT(31); // AE
2445624460
#endif
24457-
(void) ifp;
24461+
(void) ifp;
2445824462
}
2445924463

2446024464
static bool mg_tcpip_driver_stm32h_poll(struct mg_tcpip_if *ifp, bool s1) {
@@ -24488,9 +24492,12 @@ static uint32_t s_rxno;
2448824492
#if MG_ENABLE_DRIVER_MCXN
2448924493
void ETHERNET_IRQHandler(void);
2449024494
void ETHERNET_IRQHandler(void) {
24491-
#else
24495+
#elif MG_ENABLE_DRIVER_STM32H
2449224496
void ETH_IRQHandler(void);
2449324497
void ETH_IRQHandler(void) {
24498+
#else
24499+
void ETH1_IRQHandler(void);
24500+
void ETH1_IRQHandler(void) {
2449424501
#endif
2449524502
if (ETH->DMACSR & MG_BIT(6)) { // Frame received, loop
2449624503
ETH->DMACSR = MG_BIT(15) | MG_BIT(6); // Clear flag

‎mongoose.h‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3596,7 +3596,10 @@ struct mg_tcpip_driver_stm32f_data {
35963596
#if !defined(MG_ENABLE_DRIVER_MCXN)
35973597
#define MG_ENABLE_DRIVER_MCXN 0
35983598
#endif
3599-
#if MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN
3599+
#if !defined(MG_ENABLE_DRIVER_STM32N)
3600+
#define MG_ENABLE_DRIVER_STM32N 0
3601+
#endif
3602+
#if MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN || MG_ENABLE_DRIVER_STM32N
36003603

36013604
struct mg_tcpip_driver_stm32h_data {
36023605
// MDC clock divider. MDC clock is derived from HCLK, must not exceed 2.5MHz

‎src/drivers/stm32h.c‎

Lines changed: 18 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,9 @@
11
#include "net_builtin.h"
22

3-
#if MG_ENABLE_TCPIP && (MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN)
3+
#if MG_ENABLE_TCPIP && (MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN || \
4+
MG_ENABLE_DRIVER_STM32N)
45
// STM32H: vendor modded single-queue Synopsys v4.2
5-
// MCXNx4x: dual-queue Synopsys v5.2 with no hash table option
6+
// STM32N, MCXNx4x: dual-queue Synopsys v5.2 with no hash table option
67
// RT1170 ENET_QOS: quad-queue Synopsys v5.1
78
struct synopsys_enet_qos {
89
volatile uint32_t MACCR, MACECR, MACPFR, MACWTR, MACHT0R, MACHT1R,
@@ -41,17 +42,20 @@ struct synopsys_enet_qos {
4142
0x8000UL))
4243
#elif MG_ENABLE_DRIVER_MCXN
4344
#define ETH ((struct synopsys_enet_qos *) (uintptr_t) 0x40100000UL)
45+
#elif MG_ENABLE_DRIVER_STM32N
46+
#define ETH ((struct synopsys_enet_qos *) (uintptr_t) 0x48036000UL)
4447
#endif
4548

4649
#define ETH_PKT_SIZE 1540 // Max frame size
4750
#define ETH_DESC_CNT 4 // Descriptors count
4851
#define ETH_DS 4 // Descriptor size (words)
4952

50-
static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS]; // RX descriptors
51-
static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS]; // TX descriptors
52-
static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // RX ethernet buffers
53-
static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // TX ethernet buffers
54-
static struct mg_tcpip_if *s_ifp; // MIP interface
53+
#define MG_8BYTE_ALIGNED __attribute__((aligned(8)))
54+
static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS] MG_8BYTE_ALIGNED;
55+
static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS] MG_8BYTE_ALIGNED;
56+
static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_8BYTE_ALIGNED;
57+
static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_8BYTE_ALIGNED;
58+
static struct mg_tcpip_if *s_ifp; // MIP interface
5559

5660
static uint16_t eth_read_phy(uint8_t addr, uint8_t reg) {
5761
ETH->MACMDIOAR &= (0xF << 8);
@@ -102,7 +106,7 @@ static bool mg_tcpip_driver_stm32h_init(struct mg_tcpip_if *ifp) {
102106
ETH->DMASBMR |= MG_BIT(12); // AAL NOTE(scaprile): is this actually needed
103107
ETH->MACIER = 0; // Do not enable additional irq sources (reset value)
104108
ETH->MACTFCR = MG_BIT(7); // Disable zero-quanta pause
105-
#if !MG_ENABLE_DRIVER_MCXN
109+
#if MG_ENABLE_DRIVER_STM32H
106110
ETH->MACPFR = MG_BIT(10); // Perfect filtering
107111
#endif
108112
struct mg_phy phy = {eth_read_phy, eth_write_phy};
@@ -171,7 +175,7 @@ static size_t mg_tcpip_driver_stm32h_tx(const void *buf, size_t len,
171175
}
172176

173177
static void mg_tcpip_driver_stm32h_update_hash_table(struct mg_tcpip_if *ifp) {
174-
#if MG_ENABLE_DRIVER_MCXN
178+
#if MG_ENABLE_DRIVER_MCXN || MG_ENABLE_DRIVER_STM32N
175179
ETH->MACPFR = MG_BIT(4); // Pass Multicast (pass all multicast frames)
176180
#else
177181
// TODO(): read database, rebuild hash table
@@ -182,7 +186,7 @@ static void mg_tcpip_driver_stm32h_update_hash_table(struct mg_tcpip_if *ifp) {
182186
ETH->MACA1HR = (uint32_t) mcast_addr[5] << 8 | (uint32_t) mcast_addr[4];
183187
ETH->MACA1HR |= MG_BIT(31); // AE
184188
#endif
185-
(void) ifp;
189+
(void) ifp;
186190
}
187191

188192
static bool mg_tcpip_driver_stm32h_poll(struct mg_tcpip_if *ifp, bool s1) {
@@ -216,9 +220,12 @@ static uint32_t s_rxno;
216220
#if MG_ENABLE_DRIVER_MCXN
217221
void ETHERNET_IRQHandler(void);
218222
void ETHERNET_IRQHandler(void) {
219-
#else
223+
#elif MG_ENABLE_DRIVER_STM32H
220224
void ETH_IRQHandler(void);
221225
void ETH_IRQHandler(void) {
226+
#else
227+
void ETH1_IRQHandler(void);
228+
void ETH1_IRQHandler(void) {
222229
#endif
223230
if (ETH->DMACSR & MG_BIT(6)) { // Frame received, loop
224231
ETH->DMACSR = MG_BIT(15) | MG_BIT(6); // Clear flag

‎src/drivers/stm32h.h‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,10 @@
77
#if !defined(MG_ENABLE_DRIVER_MCXN)
88
#define MG_ENABLE_DRIVER_MCXN 0
99
#endif
10-
#if MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN
10+
#if !defined(MG_ENABLE_DRIVER_STM32N)
11+
#define MG_ENABLE_DRIVER_STM32N 0
12+
#endif
13+
#if MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN || MG_ENABLE_DRIVER_STM32N
1114

1215
struct mg_tcpip_driver_stm32h_data {
1316
// MDC clock divider. MDC clock is derived from HCLK, must not exceed 2.5MHz

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