[MERGE #5221 @sigatrev] arm64: use FCSEL for float instructions

Merge pull request #5221 from sigatrev:fcsel

Author: sigatrev

lib/Backend/Lower.cpp

@@ -3051,7 +3051,8 @@ Lowerer::LowerRange(IR::Instr *instrStart, IR::Instr *instrEnd, bool defaultDoFa
                 {
                     StackSym* thisSym = instr->m_func->m_symTable->Find(symid)->AsStackSym();
                     IR::RegOpnd* thisSymReg = IR::RegOpnd::New(thisSym, thisSym->GetType(), instr->m_func);
-                    IR::Instr* cmov = IR::Instr::New(LowererMD::MDSpecBlockNEOpcode, thisSymReg, thisSymReg, thisSymReg, instr->m_func);
+                    Js::OpCode specBlockOp = thisSymReg->IsFloat() ? LowererMD::MDSpecBlockFNEOpcode : LowererMD::MDSpecBlockNEOpcode;
+                    IR::Instr* cmov = IR::Instr::New(specBlockOp, thisSymReg, thisSymReg, thisSymReg, instr->m_func);
                     instr->InsertBefore(cmov);
                     m_lowererMD.Legalize(cmov);
                 } NEXT_BITSET_IN_SPARSEBV;

lib/Backend/LowerMDShared.cpp

@@ -22,6 +22,7 @@ const Js::OpCode LowererMD::MDCallOpcode = Js::OpCode::CALL;
 const Js::OpCode LowererMD::MDImulOpcode = Js::OpCode::IMUL2;
 const Js::OpCode LowererMD::MDLea = Js::OpCode::LEA;
 const Js::OpCode LowererMD::MDSpecBlockNEOpcode = Js::OpCode::CMOVNE;
+const Js::OpCode LowererMD::MDSpecBlockFNEOpcode = Js::OpCode::CMOVNE;
 
 static const int TWO_31_FLOAT = 0x4f000000;
 static const int FLOAT_INT_MIN = 0xcf000000;

lib/Backend/LowerMDShared.h

@@ -81,6 +81,7 @@ class LowererMD
     static const Js::OpCode MDImulOpcode;
     static const Js::OpCode MDLea;
     static const Js::OpCode MDSpecBlockNEOpcode;
+    static const Js::OpCode MDSpecBlockFNEOpcode;
 
     UINT FloatPrefThreshold;
 

lib/Backend/arm64/EncoderMD.cpp

@@ -761,6 +761,24 @@ int EncoderMD::EmitConvertToInt(Arm64CodeEmitter &Emitter, IR::Instr* instr, _In
     return 0;
 }
 
+template<typename _Emitter>
+int EncoderMD::EmitConditionalSelectFp(Arm64CodeEmitter &Emitter, IR::Instr *instr, int condition, _Emitter emitter)
+{
+    IR::Opnd* dst = instr->GetDst();
+    IR::Opnd* src1 = instr->GetSrc1();
+    IR::Opnd* src2 = instr->GetSrc2();
+    Assert(dst->IsRegOpnd());
+    Assert(src1->IsRegOpnd());
+    Assert(src2->IsRegOpnd());
+
+    int size = dst->GetSize();
+    Assert(size == 4 || size == 8);
+    Assert(size == src1->GetSize());
+    Assert(size == src2->GetSize());
+
+    return emitter(Emitter, this->GetFloatRegEncode(dst->AsRegOpnd()), this->GetFloatRegEncode(src1->AsRegOpnd()), this->GetRegEncode(src2->AsRegOpnd()), condition, (size == 8) ? SIZE_1D : SIZE_1S);
+}
+
 //---------------------------------------------------------------------------
 //
 // GenerateEncoding()
@@ -1180,6 +1198,14 @@ EncoderMD::GenerateEncoding(IR::Instr* instr, BYTE *pc)
         bytes = this->EmitOp2FpRegister(Emitter, instr->GetSrc1(), instr->GetSrc2(), EmitNeonFcmp);
         break;
 
+    case Js::OpCode::FCSELEQ:
+        bytes = this->EmitConditionalSelectFp(Emitter, instr, COND_EQ, EmitNeonFcsel);
+        break;
+
+    case Js::OpCode::FCSELNE:
+        bytes = this->EmitConditionalSelectFp(Emitter, instr, COND_NE, EmitNeonFcsel);
+        break;
+
     case Js::OpCode::FCVT:
         dst = instr->GetDst();
         src1 = instr->GetSrc1();

lib/Backend/arm64/EncoderMD.h

@@ -256,4 +256,5 @@ class EncoderMD
     template<typename _LoadStoreFunc> int EmitLoadStoreFp(Arm64CodeEmitter &Emitter, IR::Instr* instr, IR::Opnd* memOpnd, IR::Opnd* srcDstOpnd, _LoadStoreFunc loadStore);
     template<typename _LoadStoreFunc> int EmitLoadStoreFpPair(Arm64CodeEmitter &Emitter, IR::Instr* instr, IR::Opnd* memOpnd, IR::Opnd* srcDst1Opnd, IR::Opnd* srcDst2Opnd, _LoadStoreFunc loadStore);
     template<typename _Int32Func, typename _Uint32Func, typename _Int64Func, typename _Uint64Func> int EmitConvertToInt(Arm64CodeEmitter &Emitter, IR::Instr* instr, _Int32Func toInt32, _Uint32Func toUint32, _Int64Func toInt64, _Uint64Func toUint64);
+    template<typename _Emitter> int EmitConditionalSelectFp(Arm64CodeEmitter &Emitter, IR::Instr *instr, int condition, _Emitter emitter);
 };

lib/Backend/arm64/LowerMD.cpp

@@ -19,6 +19,7 @@ const Js::OpCode LowererMD::MDCallOpcode = Js::OpCode::Call;
 const Js::OpCode LowererMD::MDImulOpcode = Js::OpCode::MUL;
 const Js::OpCode LowererMD::MDLea = Js::OpCode::LEA;
 const Js::OpCode LowererMD::MDSpecBlockNEOpcode = Js::OpCode::CSELNE;
+const Js::OpCode LowererMD::MDSpecBlockFNEOpcode = Js::OpCode::FCSELNE;
 
 template<typename T>
 inline void Swap(T& x, T& y)

lib/Backend/arm64/LowerMD.h

@@ -62,6 +62,7 @@ class LowererMD
     static const Js::OpCode MDImulOpcode;
     static const Js::OpCode MDLea;
     static const Js::OpCode MDSpecBlockNEOpcode;
+    static const Js::OpCode MDSpecBlockFNEOpcode;
 
 public:
             void            Init(Lowerer *lowerer);

lib/Backend/arm64/MdOpCodes.h

@@ -108,6 +108,9 @@ MACRO(LDARGOUTSZ, Reg1,       0,              UNUSED,   LEGAL_REG1,     UNUSED,
 //VFP instructions:
 MACRO(FABS,        Reg2,      0,              UNUSED,   LEGAL_REG2,     UNUSED,   D___)
 MACRO(FADD,        Reg3,      0,              UNUSED,   LEGAL_REG3,     UNUSED,   D___)
+// FCSELcc src1, src2 -- select src1 if cc or src2 if not
+MACRO(FCSELEQ,     Reg3,      0,              UNUSED,   LEGAL_REG3,     UNUSED,   D___)
+MACRO(FCSELNE,     Reg3,      0,              UNUSED,   LEGAL_REG3,     UNUSED,   D___)
 MACRO(FCMP,        Reg1,      OpSideEffect,   UNUSED,   LEGAL_REG3_ND,  UNUSED,   D___)
 MACRO(FCVT,        Reg2,      0,              UNUSED,   LEGAL_REG2,     UNUSED,   D___)
 MACRO(FCVTM,       Reg2,      0,              UNUSED,   LEGAL_REG2,     UNUSED,   D___)