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ancientmodernfelicitiapicostove
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avagin
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include: add common header files for riscv64
Co-authored-by: Yixue Zhao <[email protected]> Co-authored-by: stove <[email protected]> Signed-off-by: Haorong Lu <[email protected]> --- - rebased - imported a page_size() type fix (authored by Cryolitia PukNgae) Signed-off-by: PukNgae Cryolitia <[email protected]> Signed-off-by: Alexander Mikhalitsyn <[email protected]>
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‎include/common/arch/riscv64/asm/atomic.h‎

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#ifndef __CR_ATOMIC_H__
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#define __CR_ATOMIC_H__
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typedef struct {
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int counter;
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} atomic_t;
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/* Copied from the Linux header arch/riscv/include/asm/barrier.h */
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#define nop() __asm__ __volatile__("nop")
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#define RISCV_FENCE(p, s) __asm__ __volatile__("fence " #p "," #s : : : "memory")
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/* These barriers need to enforce ordering on both devices or memory. */
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#define mb() RISCV_FENCE(iorw, iorw)
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#define rmb() RISCV_FENCE(ir, ir)
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#define wmb() RISCV_FENCE(ow, ow)
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/* These barriers do not need to enforce ordering on devices, just memory. */
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#define __smp_mb() RISCV_FENCE(rw, rw)
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#define __smp_rmb() RISCV_FENCE(r, r)
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#define __smp_wmb() RISCV_FENCE(w, w)
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#define __smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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RISCV_FENCE(rw, w); \
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WRITE_ONCE(*p, v); \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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RISCV_FENCE(r, rw); \
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___p1; \
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})
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/* Copied from the Linux kernel header arch/riscv/include/asm/atomic.h */
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static inline int atomic_read(const atomic_t *v)
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{
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return (*(volatile int *)&(v)->counter);
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}
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static inline void atomic_set(atomic_t *v, int i)
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{
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v->counter = i;
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}
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#define atomic_get atomic_read
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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int result;
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asm volatile("amoadd.w.aqrl %1, %2, %0" : "+A"(v->counter), "=r"(result) : "r"(i) : "memory");
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__smp_mb();
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return result + i;
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}
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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return atomic_add_return(-i, v);
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}
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static inline int atomic_inc(atomic_t *v)
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{
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return atomic_add_return(1, v) - 1;
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}
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static inline int atomic_add(int val, atomic_t *v)
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{
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return atomic_add_return(val, v) - val;
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}
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static inline int atomic_dec(atomic_t *v)
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{
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return atomic_sub_return(1, v) + 1;
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}
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/* true if the result is 0, or false for all other cases. */
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#define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
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#define atomic_dec_return(v) (atomic_sub_return(1, v))
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#define atomic_inc_return(v) (atomic_add_return(1, v))
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static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
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{
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unsigned long tmp;
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int oldval;
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__smp_mb();
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asm volatile("1:\n"
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" lr.w %1, %2\n"
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" bne %1, %3, 2f\n"
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" sc.w %0, %4, %2\n"
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" bnez %0, 1b\n"
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"2:"
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: "=&r"(tmp), "=&r"(oldval), "+A"(ptr->counter)
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: "r"(old), "r"(new)
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: "memory");
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__smp_mb();
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return oldval;
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}
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#endif /* __CR_ATOMIC_H__ */

‎include/common/arch/riscv64/asm/bitops.h‎

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#ifndef __CR_ASM_BITOPS_H__
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#define __CR_ASM_BITOPS_H__
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#include "common/compiler.h"
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#include "common/asm-generic/bitops.h"
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#define BITS_PER_LONG 64
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#define BIT_MASK(nr) ((1##UL) << ((nr) % BITS_PER_LONG))
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#define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
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#define __AMO(op) "amo" #op ".d"
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#define __test_and_op_bit_ord(op, mod, nr, addr, ord) \
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({ \
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unsigned long __res, __mask; \
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__mask = BIT_MASK(nr); \
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__asm__ __volatile__(__AMO(op) #ord " %0, %2, %1" \
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: "=r"(__res), "+A"(addr[BIT_WORD(nr)]) \
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: "r"(mod(__mask)) \
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: "memory"); \
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((__res & __mask) != 0); \
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})
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#define __op_bit_ord(op, mod, nr, addr, ord) \
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__asm__ __volatile__(__AMO(op) #ord " zero, %1, %0" \
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: "+A"(addr[BIT_WORD(nr)]) \
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: "r"(mod(BIT_MASK(nr))) \
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: "memory");
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#define __test_and_op_bit(op, mod, nr, addr) __test_and_op_bit_ord(op, mod, nr, addr, .aqrl)
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#define __op_bit(op, mod, nr, addr) __op_bit_ord(op, mod, nr, addr, )
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/* Bitmask modifiers */
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#define __NOP(x) (x)
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#define __NOT(x) (~(x))
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/**
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation may be reordered on other architectures than x86.
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*/
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static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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return __test_and_op_bit(or, __NOP, nr, addr);
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}
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#endif /* __CR_ASM_BITOPS_H__ */

‎include/common/arch/riscv64/asm/bitsperlong.h‎

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#ifndef __CR_BITSPERLONG_H__
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#define __CR_BITSPERLONG_H__
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#define BITS_PER_LONG 64
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#endif /* __CR_BITSPERLONG_H__ */

‎include/common/arch/riscv64/asm/linkage.h‎

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#ifndef __CR_LINKAGE_H__
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#define __CR_LINKAGE_H__
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#ifdef __ASSEMBLY__
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#define __ALIGN .align 4, 0x00
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#define __ALIGN_STR ".align 4, 0x00"
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#define GLOBAL(name) \
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.globl name; \
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name:
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#define ENTRY(name) \
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.globl name; \
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.type name, @function; \
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__ALIGN; \
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name:
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#define END(sym) .size sym, .- sym
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#endif /* __ASSEMBLY__ */
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#endif /* __CR_LINKAGE_H__ */

‎include/common/arch/riscv64/asm/page.h‎

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#ifndef __CR_ASM_PAGE_H__
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#define __CR_ASM_PAGE_H__
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#define ARCH_HAS_LONG_PAGES
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#ifndef CR_NOGLIBC
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#include <string.h> /* ffsl() */
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#include <unistd.h> /* _SC_PAGESIZE */
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extern unsigned __page_size;
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extern unsigned __page_shift;
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static inline unsigned page_size(void)
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{
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if (!__page_size)
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__page_size = sysconf(_SC_PAGESIZE);
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return __page_size;
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}
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static inline unsigned page_shift(void)
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{
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if (!__page_shift)
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__page_shift = (ffsl(page_size()) - 1);
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return __page_shift;
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}
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/*
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* Don't add ifdefs for PAGE_SIZE: if any header defines it as a constant
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* on aarch64, then we need refrain using PAGE_SIZE in criu and use
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* page_size() across sources (as it may differ on aarch64).
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*/
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#define PAGE_SIZE page_size()
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#define PAGE_MASK (~(PAGE_SIZE - 1))
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#define PAGE_SHIFT page_shift()
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#define PAGE_PFN(addr) ((addr) / PAGE_SIZE)
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#else /* CR_NOGLIBC */
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extern unsigned long page_size(void);
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#define PAGE_SIZE page_size()
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#endif /* CR_NOGLIBC */
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#endif /* __CR_ASM_PAGE_H__ */

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