images: add riscv64 core image

Co-authored-by: Yixue Zhao <[email protected]>
Co-authored-by: stove <[email protected]>
Signed-off-by: Haorong Lu <[email protected]>

Author: 3 people

images/Makefile

@@ -7,6 +7,7 @@ proto-obj-y	+= core-arm.o
 proto-obj-y	+= core-aarch64.o
 proto-obj-y	+= core-ppc64.o
 proto-obj-y	+= core-s390.o
+proto-obj-y	+= core-riscv64.o
 proto-obj-y	+= cpuinfo.o
 proto-obj-y	+= inventory.o
 proto-obj-y	+= fdinfo.o

images/core-riscv64.proto

@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: MIT
+
+syntax = "proto2";
+
+import "opts.proto";
+
+// Refer to riscv-gnu-toolchain/linux-headers/include/asm/ptrace.h
+message user_riscv64_regs_entry {
+    required uint64 pc = 1;
+    required uint64 ra = 2;
+    required uint64 sp = 3;
+    required uint64 gp = 4;
+    required uint64 tp = 5;
+    required uint64 t0 = 6;
+    required uint64 t1 = 7;
+    required uint64 t2 = 8;
+    required uint64 s0 = 9;
+    required uint64 s1 = 10;
+    required uint64 a0 = 11;
+    required uint64 a1 = 12;
+    required uint64 a2 = 13;
+    required uint64 a3 = 14;
+    required uint64 a4 = 15;
+    required uint64 a5 = 16;
+    required uint64 a6 = 17;
+    required uint64 a7 = 18;
+    required uint64 s2 = 19;
+    required uint64 s3 = 20;
+    required uint64 s4 = 21;
+    required uint64 s5 = 22;
+    required uint64 s6 = 23;
+    required uint64 s7 = 24;
+    required uint64 s8 = 25;
+    required uint64 s9 = 26;
+    required uint64 s10 = 27;
+    required uint64 s11 = 28;
+    required uint64 t3 = 29;
+    required uint64 t4 = 30;
+    required uint64 t5 = 31;
+    required uint64 t6 = 32;    
+}
+
+message user_riscv64_d_ext_entry {
+    repeated uint64 f = 1;
+    required uint32 fcsr = 2;
+}
+
+message thread_info_riscv64 {
+	required uint64				clear_tid_addr	= 1[(criu).hex = true];
+	required uint64				tls		= 2;
+	required user_riscv64_regs_entry	gpregs		= 3[(criu).hex = true];
+	required user_riscv64_d_ext_entry	fpsimd		= 4;
+}

images/core.proto

@@ -9,6 +9,7 @@ import "core-ppc64.proto";
 import "core-s390.proto";
 import "core-mips.proto";
 import "core-loongarch64.proto";
+import "core-riscv64.proto";
 
 import "rlimit.proto";
 import "timer.proto";
@@ -126,6 +127,7 @@ message core_entry {
 		S390		= 5;
 		MIPS		= 6;
 		LOONGARCH64		= 7;
+		RISCV64		= 8;
 	}
 
 	required march			mtype		= 1;
@@ -136,6 +138,7 @@ message core_entry {
 	optional thread_info_s390	ti_s390		= 10;
 	optional thread_info_mips	ti_mips		= 11;
 	optional thread_info_loongarch64	ti_loongarch64  = 12;
+	optional thread_info_riscv64	ti_riscv64	= 13;
 
 	optional task_core_entry	tc		= 3;
 	optional task_kobj_ids_entry	ids		= 4;