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RKSimonRKSimon
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[Hexagon] clr_set_toggle.ll - regenerate test checks
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‎llvm/test/CodeGen/Hexagon/clr_set_toggle.ll‎

Lines changed: 171 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,21 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
12
; RUN: llc -mtriple=hexagon -hexagon-bit=0 < %s | FileCheck %s
23
; Optimized bitwise operations.
34

45
define i32 @my_clrbit(i32 %x) nounwind {
6+
; CHECK-LABEL: my_clrbit:
7+
; CHECK: // %bb.0: // %entry
8+
; CHECK-NEXT: {
9+
; CHECK-NEXT: r0 = clrbit(r0,#31)
10+
; CHECK-NEXT: r1 = r0
11+
; CHECK-NEXT: r29 = add(r29,#-8)
12+
; CHECK-NEXT: }
13+
; CHECK-NEXT: {
14+
; CHECK-NEXT: r29 = add(r29,#8)
15+
; CHECK-NEXT: jumpr r31
16+
; CHECK-NEXT: memw(r29+#4) = r1
17+
; CHECK-NEXT: }
518
entry:
6-
; CHECK-LABEL: my_clrbit
7-
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31)
819
%x.addr = alloca i32, align 4
920
store i32 %x, ptr %x.addr, align 4
1021
%0 = load i32, ptr %x.addr, align 4
@@ -13,9 +24,18 @@ entry:
1324
}
1425

1526
define i64 @my_clrbit2(i64 %x) nounwind {
27+
; CHECK-LABEL: my_clrbit2:
28+
; CHECK: // %bb.0: // %entry
29+
; CHECK-NEXT: {
30+
; CHECK-NEXT: r29 = add(r29,#-8)
31+
; CHECK-NEXT: }
32+
; CHECK-NEXT: {
33+
; CHECK-NEXT: r0 = clrbit(r0,#31)
34+
; CHECK-NEXT: jumpr r31
35+
; CHECK-NEXT: r29 = add(r29,#8)
36+
; CHECK-NEXT: memd(r29+#0) = r1:0
37+
; CHECK-NEXT: }
1638
entry:
17-
; CHECK-LABEL: my_clrbit2
18-
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31)
1939
%x.addr = alloca i64, align 8
2040
store i64 %x, ptr %x.addr, align 8
2141
%0 = load i64, ptr %x.addr, align 8
@@ -24,9 +44,18 @@ entry:
2444
}
2545

2646
define i64 @my_clrbit3(i64 %x) nounwind {
47+
; CHECK-LABEL: my_clrbit3:
48+
; CHECK: // %bb.0: // %entry
49+
; CHECK-NEXT: {
50+
; CHECK-NEXT: r29 = add(r29,#-8)
51+
; CHECK-NEXT: }
52+
; CHECK-NEXT: {
53+
; CHECK-NEXT: r1 = clrbit(r1,#31)
54+
; CHECK-NEXT: jumpr r31
55+
; CHECK-NEXT: r29 = add(r29,#8)
56+
; CHECK-NEXT: memd(r29+#0) = r1:0
57+
; CHECK-NEXT: }
2758
entry:
28-
; CHECK-LABEL: my_clrbit3
29-
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31)
3059
%x.addr = alloca i64, align 8
3160
store i64 %x, ptr %x.addr, align 8
3261
%0 = load i64, ptr %x.addr, align 8
@@ -35,9 +64,19 @@ entry:
3564
}
3665

3766
define i32 @my_clrbit4(i32 %x) nounwind {
67+
; CHECK-LABEL: my_clrbit4:
68+
; CHECK: // %bb.0: // %entry
69+
; CHECK-NEXT: {
70+
; CHECK-NEXT: r0 = clrbit(r0,#13)
71+
; CHECK-NEXT: r1 = r0
72+
; CHECK-NEXT: r29 = add(r29,#-8)
73+
; CHECK-NEXT: }
74+
; CHECK-NEXT: {
75+
; CHECK-NEXT: r29 = add(r29,#8)
76+
; CHECK-NEXT: jumpr r31
77+
; CHECK-NEXT: memw(r29+#4) = r1
78+
; CHECK-NEXT: }
3879
entry:
39-
; CHECK-LABEL: my_clrbit4
40-
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#13)
4180
%x.addr = alloca i32, align 4
4281
store i32 %x, ptr %x.addr, align 4
4382
%0 = load i32, ptr %x.addr, align 4
@@ -46,9 +85,18 @@ entry:
4685
}
4786

4887
define i64 @my_clrbit5(i64 %x) nounwind {
88+
; CHECK-LABEL: my_clrbit5:
89+
; CHECK: // %bb.0: // %entry
90+
; CHECK-NEXT: {
91+
; CHECK-NEXT: r29 = add(r29,#-8)
92+
; CHECK-NEXT: }
93+
; CHECK-NEXT: {
94+
; CHECK-NEXT: r0 = clrbit(r0,#13)
95+
; CHECK-NEXT: jumpr r31
96+
; CHECK-NEXT: r29 = add(r29,#8)
97+
; CHECK-NEXT: memd(r29+#0) = r1:0
98+
; CHECK-NEXT: }
4999
entry:
50-
; CHECK-LABEL: my_clrbit5
51-
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#13)
52100
%x.addr = alloca i64, align 8
53101
store i64 %x, ptr %x.addr, align 8
54102
%0 = load i64, ptr %x.addr, align 8
@@ -57,9 +105,18 @@ entry:
57105
}
58106

59107
define i64 @my_clrbit6(i64 %x) nounwind {
108+
; CHECK-LABEL: my_clrbit6:
109+
; CHECK: // %bb.0: // %entry
110+
; CHECK-NEXT: {
111+
; CHECK-NEXT: r29 = add(r29,#-8)
112+
; CHECK-NEXT: }
113+
; CHECK-NEXT: {
114+
; CHECK-NEXT: r1 = clrbit(r1,#27)
115+
; CHECK-NEXT: jumpr r31
116+
; CHECK-NEXT: r29 = add(r29,#8)
117+
; CHECK-NEXT: memd(r29+#0) = r1:0
118+
; CHECK-NEXT: }
60119
entry:
61-
; CHECK-LABEL: my_clrbit6
62-
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#27)
63120
%x.addr = alloca i64, align 8
64121
store i64 %x, ptr %x.addr, align 8
65122
%0 = load i64, ptr %x.addr, align 8
@@ -68,9 +125,18 @@ entry:
68125
}
69126

70127
define zeroext i16 @my_setbit(i16 zeroext %crc) nounwind {
128+
; CHECK-LABEL: my_setbit:
129+
; CHECK: // %bb.0: // %entry
130+
; CHECK-NEXT: {
131+
; CHECK-NEXT: r0 = setbit(r0,#15)
132+
; CHECK-NEXT: r29 = add(r29,#-8)
133+
; CHECK-NEXT: }
134+
; CHECK-NEXT: {
135+
; CHECK-NEXT: r29 = add(r29,#8)
136+
; CHECK-NEXT: jumpr r31
137+
; CHECK-NEXT: memh(r29+#6) = r0
138+
; CHECK-NEXT: }
71139
entry:
72-
; CHECK-LABEL: my_setbit
73-
; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#15)
74140
%crc.addr = alloca i16, align 2
75141
store i16 %crc, ptr %crc.addr, align 2
76142
%0 = load i16, ptr %crc.addr, align 2
@@ -83,9 +149,19 @@ entry:
83149
}
84150

85151
define i32 @my_setbit2(i32 %x) nounwind {
152+
; CHECK-LABEL: my_setbit2:
153+
; CHECK: // %bb.0: // %entry
154+
; CHECK-NEXT: {
155+
; CHECK-NEXT: r0 = setbit(r0,#15)
156+
; CHECK-NEXT: r1 = r0
157+
; CHECK-NEXT: r29 = add(r29,#-8)
158+
; CHECK-NEXT: }
159+
; CHECK-NEXT: {
160+
; CHECK-NEXT: r29 = add(r29,#8)
161+
; CHECK-NEXT: jumpr r31
162+
; CHECK-NEXT: memw(r29+#4) = r1
163+
; CHECK-NEXT: }
86164
entry:
87-
; CHECK-LABEL: my_setbit2
88-
; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#15)
89165
%x.addr = alloca i32, align 4
90166
store i32 %x, ptr %x.addr, align 4
91167
%0 = load i32, ptr %x.addr, align 4
@@ -94,9 +170,18 @@ entry:
94170
}
95171

96172
define i64 @my_setbit3(i64 %x) nounwind {
173+
; CHECK-LABEL: my_setbit3:
174+
; CHECK: // %bb.0: // %entry
175+
; CHECK-NEXT: {
176+
; CHECK-NEXT: r29 = add(r29,#-8)
177+
; CHECK-NEXT: }
178+
; CHECK-NEXT: {
179+
; CHECK-NEXT: r0 = setbit(r0,#15)
180+
; CHECK-NEXT: jumpr r31
181+
; CHECK-NEXT: r29 = add(r29,#8)
182+
; CHECK-NEXT: memd(r29+#0) = r1:0
183+
; CHECK-NEXT: }
97184
entry:
98-
; CHECK-LABEL: my_setbit3
99-
; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#15)
100185
%x.addr = alloca i64, align 8
101186
store i64 %x, ptr %x.addr, align 8
102187
%0 = load i64, ptr %x.addr, align 8
@@ -105,9 +190,19 @@ entry:
105190
}
106191

107192
define i32 @my_setbit4(i32 %x) nounwind {
193+
; CHECK-LABEL: my_setbit4:
194+
; CHECK: // %bb.0: // %entry
195+
; CHECK-NEXT: {
196+
; CHECK-NEXT: r0 = setbit(r0,#31)
197+
; CHECK-NEXT: r1 = r0
198+
; CHECK-NEXT: r29 = add(r29,#-8)
199+
; CHECK-NEXT: }
200+
; CHECK-NEXT: {
201+
; CHECK-NEXT: r29 = add(r29,#8)
202+
; CHECK-NEXT: jumpr r31
203+
; CHECK-NEXT: memw(r29+#4) = r1
204+
; CHECK-NEXT: }
108205
entry:
109-
; CHECK-LABEL: my_setbit4
110-
; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#31)
111206
%x.addr = alloca i32, align 4
112207
store i32 %x, ptr %x.addr, align 4
113208
%0 = load i32, ptr %x.addr, align 4
@@ -116,9 +211,18 @@ entry:
116211
}
117212

118213
define i64 @my_setbit5(i64 %x) nounwind {
214+
; CHECK-LABEL: my_setbit5:
215+
; CHECK: // %bb.0: // %entry
216+
; CHECK-NEXT: {
217+
; CHECK-NEXT: r29 = add(r29,#-8)
218+
; CHECK-NEXT: }
219+
; CHECK-NEXT: {
220+
; CHECK-NEXT: r1 = setbit(r1,#13)
221+
; CHECK-NEXT: jumpr r31
222+
; CHECK-NEXT: r29 = add(r29,#8)
223+
; CHECK-NEXT: memd(r29+#0) = r1:0
224+
; CHECK-NEXT: }
119225
entry:
120-
; CHECK-LABEL: my_setbit5
121-
; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#13)
122226
%x.addr = alloca i64, align 8
123227
store i64 %x, ptr %x.addr, align 8
124228
%0 = load i64, ptr %x.addr, align 8
@@ -127,9 +231,18 @@ entry:
127231
}
128232

129233
define zeroext i16 @my_togglebit(i16 zeroext %crc) nounwind {
234+
; CHECK-LABEL: my_togglebit:
235+
; CHECK: // %bb.0: // %entry
236+
; CHECK-NEXT: {
237+
; CHECK-NEXT: r0 = togglebit(r0,#15)
238+
; CHECK-NEXT: r29 = add(r29,#-8)
239+
; CHECK-NEXT: }
240+
; CHECK-NEXT: {
241+
; CHECK-NEXT: r29 = add(r29,#8)
242+
; CHECK-NEXT: jumpr r31
243+
; CHECK-NEXT: memh(r29+#6) = r0
244+
; CHECK-NEXT: }
130245
entry:
131-
; CHECK-LABEL: my_togglebit
132-
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#15)
133246
%crc.addr = alloca i16, align 2
134247
store i16 %crc, ptr %crc.addr, align 2
135248
%0 = load i16, ptr %crc.addr, align 2
@@ -142,9 +255,19 @@ entry:
142255
}
143256

144257
define i32 @my_togglebit2(i32 %x) nounwind {
258+
; CHECK-LABEL: my_togglebit2:
259+
; CHECK: // %bb.0: // %entry
260+
; CHECK-NEXT: {
261+
; CHECK-NEXT: r0 = togglebit(r0,#15)
262+
; CHECK-NEXT: r1 = r0
263+
; CHECK-NEXT: r29 = add(r29,#-8)
264+
; CHECK-NEXT: }
265+
; CHECK-NEXT: {
266+
; CHECK-NEXT: r29 = add(r29,#8)
267+
; CHECK-NEXT: jumpr r31
268+
; CHECK-NEXT: memw(r29+#4) = r1
269+
; CHECK-NEXT: }
145270
entry:
146-
; CHECK-LABEL: my_togglebit2
147-
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#15)
148271
%x.addr = alloca i32, align 4
149272
store i32 %x, ptr %x.addr, align 4
150273
%0 = load i32, ptr %x.addr, align 4
@@ -153,9 +276,18 @@ entry:
153276
}
154277

155278
define i64 @my_togglebit3(i64 %x) nounwind {
279+
; CHECK-LABEL: my_togglebit3:
280+
; CHECK: // %bb.0: // %entry
281+
; CHECK-NEXT: {
282+
; CHECK-NEXT: r29 = add(r29,#-8)
283+
; CHECK-NEXT: }
284+
; CHECK-NEXT: {
285+
; CHECK-NEXT: r0 = togglebit(r0,#15)
286+
; CHECK-NEXT: jumpr r31
287+
; CHECK-NEXT: r29 = add(r29,#8)
288+
; CHECK-NEXT: memd(r29+#0) = r1:0
289+
; CHECK-NEXT: }
156290
entry:
157-
; CHECK-LABEL: my_togglebit3
158-
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#15)
159291
%x.addr = alloca i64, align 8
160292
store i64 %x, ptr %x.addr, align 8
161293
%0 = load i64, ptr %x.addr, align 8
@@ -164,9 +296,18 @@ entry:
164296
}
165297

166298
define i64 @my_togglebit4(i64 %x) nounwind {
299+
; CHECK-LABEL: my_togglebit4:
300+
; CHECK: // %bb.0: // %entry
301+
; CHECK-NEXT: {
302+
; CHECK-NEXT: r29 = add(r29,#-8)
303+
; CHECK-NEXT: }
304+
; CHECK-NEXT: {
305+
; CHECK-NEXT: r1 = togglebit(r1,#20)
306+
; CHECK-NEXT: jumpr r31
307+
; CHECK-NEXT: r29 = add(r29,#8)
308+
; CHECK-NEXT: memd(r29+#0) = r1:0
309+
; CHECK-NEXT: }
167310
entry:
168-
; CHECK-LABEL: my_togglebit4
169-
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#20)
170311
%x.addr = alloca i64, align 8
171312
store i64 %x, ptr %x.addr, align 8
172313
%0 = load i64, ptr %x.addr, align 8

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