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alaindargelasalaindargelas
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const_assign const bug
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9 files changed

+181
-24
lines changed

9 files changed

+181
-24
lines changed

‎CMakeLists.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ cmake_minimum_required(VERSION 3.20 FATAL_ERROR)
55
# Version changes whenever some new features accumulated, or the
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# grammar or the cache format changes to make sure caches
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# are invalidated.
8-
project(SURELOG VERSION 1.61)
8+
project(SURELOG VERSION 1.62)
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1010
# Detect build type, fallback to release and throw a warning if use didn't
1111
# specify any

‎tests/HierBitSlice/HierBitSlice.log‎

Lines changed: 94 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -14182,6 +14182,53 @@ design: (work@int_execute_stage)
1418214182
|vpiParent:
1418314183
\_gen_scope: (work@int_execute_stage.lane_alu_gen[0])
1418414184
|vpiRhs:
14185+
\_operation: , line:120:43, endln:120:88
14186+
|vpiParent:
14187+
\_cont_assign: , line:120:20, endln:120:88
14188+
|vpiOpType:11
14189+
|vpiOperand:
14190+
\_operation: , line:120:43, endln:120:64
14191+
|vpiParent:
14192+
\_operation: , line:120:43, endln:120:88
14193+
|vpiOpType:33
14194+
|vpiOperand:
14195+
\_constant: , line:120:44, endln:120:48
14196+
|vpiParent:
14197+
\_operation: , line:120:43, endln:120:64
14198+
|vpiDecompile:1'b0
14199+
|vpiSize:1
14200+
|BIN:0
14201+
|vpiConstType:3
14202+
|vpiOperand:
14203+
\_ref_obj: (work@int_execute_stage.lane_alu_gen[0].lane_operand1), line:120:50, endln:120:63
14204+
|vpiParent:
14205+
\_operation: , line:120:43, endln:120:64
14206+
|vpiName:lane_operand1
14207+
|vpiFullName:work@int_execute_stage.lane_alu_gen[0].lane_operand1
14208+
|vpiActual:
14209+
\_logic_var: (work@int_execute_stage.lane_alu_gen[0].lane_operand1), line:101:22, endln:101:35
14210+
|vpiOperand:
14211+
\_operation: , line:120:67, endln:120:88
14212+
|vpiParent:
14213+
\_operation: , line:120:43, endln:120:88
14214+
|vpiOpType:33
14215+
|vpiOperand:
14216+
\_constant: , line:120:68, endln:120:72
14217+
|vpiParent:
14218+
\_operation: , line:120:67, endln:120:88
14219+
|vpiDecompile:1'b0
14220+
|vpiSize:1
14221+
|BIN:0
14222+
|vpiConstType:3
14223+
|vpiOperand:
14224+
\_ref_obj: (work@int_execute_stage.lane_alu_gen[0].lane_operand2), line:120:74, endln:120:87
14225+
|vpiParent:
14226+
\_operation: , line:120:67, endln:120:88
14227+
|vpiName:lane_operand2
14228+
|vpiFullName:work@int_execute_stage.lane_alu_gen[0].lane_operand2
14229+
|vpiActual:
14230+
\_logic_var: (work@int_execute_stage.lane_alu_gen[0].lane_operand2), line:102:22, endln:102:35
14231+
|vpiLhs:
1418514232
\_operation: , line:120:21, endln:120:27
1418614233
|vpiParent:
1418714234
\_cont_assign: , line:120:20, endln:120:88
@@ -14202,8 +14249,6 @@ design: (work@int_execute_stage)
1420214249
|vpiFullName:work@int_execute_stage.lane_alu_gen[0].difference
1420314250
|vpiActual:
1420414251
\_logic_var: (work@int_execute_stage.lane_alu_gen[0].difference), line:104:22, endln:104:32
14205-
|vpiLhs:
14206-
\_operation: , line:120:21, endln:120:27
1420714252
|vpiContAssign:
1420814253
\_cont_assign: , line:121:20, endln:121:45
1420914254
|vpiParent:
@@ -19549,6 +19594,53 @@ design: (work@int_execute_stage)
1954919594
|vpiParent:
1955019595
\_gen_scope: (work@int_execute_stage.lane_alu_gen[1])
1955119596
|vpiRhs:
19597+
\_operation: , line:120:43, endln:120:88
19598+
|vpiParent:
19599+
\_cont_assign: , line:120:20, endln:120:88
19600+
|vpiOpType:11
19601+
|vpiOperand:
19602+
\_operation: , line:120:43, endln:120:64
19603+
|vpiParent:
19604+
\_operation: , line:120:43, endln:120:88
19605+
|vpiOpType:33
19606+
|vpiOperand:
19607+
\_constant: , line:120:44, endln:120:48
19608+
|vpiParent:
19609+
\_operation: , line:120:43, endln:120:64
19610+
|vpiDecompile:1'b0
19611+
|vpiSize:1
19612+
|BIN:0
19613+
|vpiConstType:3
19614+
|vpiOperand:
19615+
\_ref_obj: (work@int_execute_stage.lane_alu_gen[1].lane_operand1), line:120:50, endln:120:63
19616+
|vpiParent:
19617+
\_operation: , line:120:43, endln:120:64
19618+
|vpiName:lane_operand1
19619+
|vpiFullName:work@int_execute_stage.lane_alu_gen[1].lane_operand1
19620+
|vpiActual:
19621+
\_logic_var: (work@int_execute_stage.lane_alu_gen[1].lane_operand1), line:101:22, endln:101:35
19622+
|vpiOperand:
19623+
\_operation: , line:120:67, endln:120:88
19624+
|vpiParent:
19625+
\_operation: , line:120:43, endln:120:88
19626+
|vpiOpType:33
19627+
|vpiOperand:
19628+
\_constant: , line:120:68, endln:120:72
19629+
|vpiParent:
19630+
\_operation: , line:120:67, endln:120:88
19631+
|vpiDecompile:1'b0
19632+
|vpiSize:1
19633+
|BIN:0
19634+
|vpiConstType:3
19635+
|vpiOperand:
19636+
\_ref_obj: (work@int_execute_stage.lane_alu_gen[1].lane_operand2), line:120:74, endln:120:87
19637+
|vpiParent:
19638+
\_operation: , line:120:67, endln:120:88
19639+
|vpiName:lane_operand2
19640+
|vpiFullName:work@int_execute_stage.lane_alu_gen[1].lane_operand2
19641+
|vpiActual:
19642+
\_logic_var: (work@int_execute_stage.lane_alu_gen[1].lane_operand2), line:102:22, endln:102:35
19643+
|vpiLhs:
1955219644
\_operation: , line:120:21, endln:120:27
1955319645
|vpiParent:
1955419646
\_cont_assign: , line:120:20, endln:120:88
@@ -19569,8 +19661,6 @@ design: (work@int_execute_stage)
1956919661
|vpiFullName:work@int_execute_stage.lane_alu_gen[1].difference
1957019662
|vpiActual:
1957119663
\_logic_var: (work@int_execute_stage.lane_alu_gen[1].difference), line:104:22, endln:104:32
19572-
|vpiLhs:
19573-
\_operation: , line:120:21, endln:120:27
1957419664
|vpiContAssign:
1957519665
\_cont_assign: , line:121:20, endln:121:45
1957619666
|vpiParent:

‎tests/IndexPartSel/IndexPartSel.log‎

Lines changed: 33 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -430,6 +430,22 @@ design: (work@dut)
430430
|vpiParent:
431431
\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10
432432
|vpiRhs:
433+
\_bit_select: ([email protected]_wrap), line:6:33, endln:6:49
434+
|vpiParent:
435+
\_ref_obj: ([email protected]_wrap)
436+
|vpiParent:
437+
\_cont_assign: , line:6:8, endln:6:49
438+
|vpiName:hw2reg_wrap
439+
|vpiFullName:[email protected]_wrap
440+
|vpiActual:
441+
\_logic_net: ([email protected]_wrap), line:3:14, endln:3:25
442+
|vpiName:hw2reg_wrap
443+
|vpiFullName:[email protected]_wrap
444+
|vpiIndex:
445+
\_constant: , line:6:45, endln:6:48
446+
|vpiActual:
447+
\_logic_net: ([email protected]_wrap), line:3:14, endln:3:25
448+
|vpiLhs:
433449
\_operation: , line:6:9, endln:6:29
434450
|vpiParent:
435451
\_cont_assign: , line:6:8, endln:6:49
@@ -450,13 +466,28 @@ design: (work@dut)
450466
\_constant: , line:6:27, endln:6:28
451467
|vpiActual:
452468
\_logic_net: ([email protected]_bitselect), line:5:13, endln:5:30
453-
|vpiLhs:
454-
\_operation: , line:6:9, endln:6:29
455469
|vpiContAssign:
456470
\_cont_assign: , line:7:8, endln:7:71
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|vpiParent:
458472
\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10
459473
|vpiRhs:
474+
\_indexed_part_select: , line:7:63, endln:7:70
475+
|vpiParent:
476+
\_ref_obj: hw2reg_wrap ([email protected]_wrap)
477+
|vpiParent:
478+
\_cont_assign: , line:7:8, endln:7:71
479+
|vpiName:hw2reg_wrap
480+
|vpiFullName:[email protected]_wrap
481+
|vpiDefName:hw2reg_wrap
482+
|vpiActual:
483+
\_logic_net: ([email protected]_wrap), line:3:14, endln:3:25
484+
|vpiConstantSelect:1
485+
|vpiIndexedPartSelectType:2
486+
|vpiBaseExpr:
487+
\_constant: , line:7:63, endln:7:66
488+
|vpiWidthExpr:
489+
\_constant: , line:7:68, endln:7:70
490+
|vpiLhs:
460491
\_operation: , line:7:9, endln:7:47
461492
|vpiParent:
462493
\_cont_assign: , line:7:8, endln:7:71
@@ -478,8 +509,6 @@ design: (work@dut)
478509
\_constant: , line:7:40, endln:7:42
479510
|vpiWidthExpr:
480511
\_constant: , line:7:44, endln:7:46
481-
|vpiLhs:
482-
\_operation: , line:7:9, endln:7:47
483512
===================
484513
[ FATAL] : 0
485514
[ SYNTAX] : 0

‎tests/MBAdder/MBadder.log‎

Lines changed: 34 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -960,6 +960,40 @@ design: (work@MultibitAdder)
960960
|vpiParent:
961961
\_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10
962962
|vpiRhs:
963+
\_operation: , line:6:20, endln:6:27
964+
|vpiParent:
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\_cont_assign: , line:6:9, endln:6:27
966+
|vpiOpType:24
967+
|vpiOperand:
968+
\_operation: , line:6:20, endln:6:23
969+
|vpiParent:
970+
\_operation: , line:6:20, endln:6:27
971+
|vpiOpType:24
972+
|vpiOperand:
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\_ref_obj: ([email protected]), line:6:20, endln:6:21
974+
|vpiParent:
975+
\_operation: , line:6:20, endln:6:23
976+
|vpiName:a
977+
|vpiFullName:[email protected]
978+
|vpiActual:
979+
\_logic_net: ([email protected]), line:1:22, endln:1:23
980+
|vpiOperand:
981+
\_ref_obj: ([email protected]), line:6:22, endln:6:23
982+
|vpiParent:
983+
\_operation: , line:6:20, endln:6:23
984+
|vpiName:b
985+
|vpiFullName:[email protected]
986+
|vpiActual:
987+
\_logic_net: ([email protected]), line:1:24, endln:1:25
988+
|vpiOperand:
989+
\_ref_obj: ([email protected]), line:6:24, endln:6:27
990+
|vpiParent:
991+
\_operation: , line:6:20, endln:6:27
992+
|vpiName:cin
993+
|vpiFullName:[email protected]
994+
|vpiActual:
995+
\_logic_net: ([email protected]), line:1:26, endln:1:29
996+
|vpiLhs:
963997
\_operation: , line:6:10, endln:6:14
964998
|vpiParent:
965999
\_cont_assign: , line:6:9, endln:6:27
@@ -980,8 +1014,6 @@ design: (work@MultibitAdder)
9801014
|vpiFullName:[email protected]
9811015
|vpiActual:
9821016
\_logic_net: ([email protected]), line:1:30, endln:1:33
983-
|vpiLhs:
984-
\_operation: , line:6:10, endln:6:14
9851017
===================
9861018
[ FATAL] : 0
9871019
[ SYNTAX] : 0

‎tests/PartSelectParent/PartSelectParent.log‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -396,6 +396,8 @@ design: (work@top)
396396
|vpiParent:
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\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10
398398
|vpiRhs:
399+
\_constant: , line:7:24, endln:7:29
400+
|vpiLhs:
399401
\_operation: , line:7:14, endln:7:20
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|vpiParent:
401403
\_cont_assign: , line:7:13, endln:7:29
@@ -428,8 +430,6 @@ design: (work@top)
428430
|vpiSize:64
429431
|UINT:0
430432
|vpiConstType:9
431-
|vpiLhs:
432-
\_operation: , line:7:14, endln:7:20
433433
===================
434434
[ FATAL] : 0
435435
[ SYNTAX] : 0

‎tests/UnitConcat/UnitConcat.log‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,14 @@ design: (work@dut)
5252
|vpiParent:
5353
\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitConcat/top.sv, line:1:1, endln:8:10
5454
|vpiRhs:
55+
\_ref_obj: ([email protected]), line:6:20, endln:6:23
56+
|vpiParent:
57+
\_cont_assign: , line:3:10, endln:6:23
58+
|vpiName:irq
59+
|vpiFullName:[email protected]
60+
|vpiActual:
61+
\_logic_net: (irq)
62+
|vpiLhs:
5563
\_operation: , line:3:11, endln:3:24
5664
|vpiParent:
5765
\_cont_assign: , line:3:10, endln:6:23
@@ -88,8 +96,6 @@ design: (work@dut)
8896
|vpiFullName:[email protected]_classa_o
8997
|vpiActual:
9098
\_logic_net: (intr_classa_o)
91-
|vpiLhs:
92-
\_operation: , line:3:11, endln:3:24
9399
|uhdmtopModules:
94100
\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitConcat/top.sv, line:1:1, endln:8:10
95101
|vpiName:work@dut

‎third_party/UHDM‎

‎third_party/googletest‎

‎third_party/tests/CoresSweRVMP/CoresSweRVMP.log‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -115,7 +115,7 @@ PP CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv
115115
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/CoresSweRVMP/design/lib/axi4_to_ahb.sv".
116116

117117
Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; cmake -G "Unix Makefiles" .; make -j 16
118-
-- Configuring done (0.1s)
118+
-- Configuring done (0.0s)
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-- Generating done (0.0s)
120120
-- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
121121
[ 6%] Generating 10_lsu_bus_intf.sv
@@ -124,16 +124,16 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
124124
[ 25%] Generating 13_ifu_mem_ctl.sv
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[ 31%] Generating 14_mem_lib.sv
126126
[ 37%] Generating 15_exu.sv
127-
[ 43%] Generating 1_lsu_stbuf.sv
128-
[ 50%] Generating 16_dec_decode_ctl.sv
129-
[ 56%] Generating 2_ahb_to_axi4.sv
130-
[ 62%] Generating 3_rvjtag_tap.sv
127+
[ 43%] Generating 16_dec_decode_ctl.sv
128+
[ 50%] Generating 1_lsu_stbuf.sv
129+
[ 56%] Generating 3_rvjtag_tap.sv
130+
[ 62%] Generating 2_ahb_to_axi4.sv
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[ 68%] Generating 4_dec_tlu_ctl.sv
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[ 75%] Generating 5_lsu_bus_buffer.sv
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[ 81%] Generating 6_dbg.sv
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[ 87%] Generating 7_axi4_to_ahb.sv
135-
[ 93%] Generating 9_tb_top.sv
136-
[100%] Generating 8_ifu_aln_ctl.sv
135+
[ 93%] Generating 8_ifu_aln_ctl.sv
136+
[100%] Generating 9_tb_top.sv
137137
[100%] Built target Parse
138138
Surelog parsing status: 0
139139
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv".

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