@@ -115,25 +115,25 @@ PP CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv
115115[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/CoresSweRVMP/design/lib/axi4_to_ahb.sv".
116116
117117Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; cmake -G "Unix Makefiles" .; make -j 16
118- -- Configuring done (0.0s )
118+ -- Configuring done (0.1s )
119119-- Generating done (0.0s)
120120-- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
121- [ 6%] Generating 15_exu .sv
122- [ 12%] Generating 13_ifu_mem_ctl .sv
123- [ 18%] Generating 16_dec_decode_ctl .sv
124- [ 25%] Generating 10_lsu_bus_intf .sv
125- [ 31%] Generating 11_ifu_bp_ctl .sv
126- [ 37%] Generating 12_beh_lib .sv
127- [ 43%] Generating 14_mem_lib .sv
121+ [ 6%] Generating 10_lsu_bus_intf .sv
122+ [ 12%] Generating 11_ifu_bp_ctl .sv
123+ [ 18%] Generating 13_ifu_mem_ctl .sv
124+ [ 25%] Generating 12_beh_lib .sv
125+ [ 31%] Generating 14_mem_lib .sv
126+ [ 37%] Generating 15_exu .sv
127+ [ 43%] Generating 16_dec_decode_ctl .sv
128128[ 50%] Generating 1_lsu_stbuf.sv
129129[ 56%] Generating 2_ahb_to_axi4.sv
130130[ 62%] Generating 3_rvjtag_tap.sv
131131[ 68%] Generating 4_dec_tlu_ctl.sv
132132[ 75%] Generating 5_lsu_bus_buffer.sv
133133[ 81%] Generating 6_dbg.sv
134134[ 87%] Generating 7_axi4_to_ahb.sv
135- [ 93%] Generating 8_ifu_aln_ctl .sv
136- [100%] Generating 9_tb_top .sv
135+ [ 93%] Generating 9_tb_top .sv
136+ [100%] Generating 8_ifu_aln_ctl .sv
137137[100%] Built target Parse
138138Surelog parsing status: 0
139139[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv".
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