Model class hierarchy change for select nodes

bit_select, and other select classes use the vpiParent pointer (as refobj) to
provide parent and actual_group access. bit_select.vpiParent.vpiParent is the
"true" parent of the bit_select and bit_select.vpiParent.actual_group is
access to the actual. However, vpiParent edges in the graph are weak
references and ignored for all traversals (including VpiListener,
UhdmListener, and vpi_visitor). Tail of parent edges are missing in the UHDM
output since the nodes are ignored. The traversal mode also generate
unexpected results during runtime because of the ignored edges.

Changing the hierarchy so that ref_obj works as a base (intermediate class in
the class hierarchy, yet instantiable) and other select classes (including
bit_select, indexed_part_select, part_select, and var_select) are subclasses
of ref_obj. This gives access to ref_obj.actual_group and ref.vpiParent can be
used for the usual parenting purposes.

Author: hs-apotell

include/Surelog/DesignCompile/CompileHelper.h

@@ -154,7 +154,8 @@ class CompileHelper final {
                           ValuedComponentI* instance);
 
   UHDM::any* compileTfCall(DesignComponent* component, const FileContent* fC,
-                           NodeId Tf_call_stmt, CompileDesign* compileDesign);
+                           NodeId Tf_call_stmt, CompileDesign* compileDesign,
+                           UHDM::any* pexpr);
 
   UHDM::VectorOfany* compileTfCallArguments(
       DesignComponent* component, const FileContent* fC, NodeId Arg_list_node,