@@ -118,18 +118,18 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
118118-- Configuring done (0.0s)
119119-- Generating done (0.0s)
120120-- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
121- [ 6%] Generating 16_dec_decode_ctl .sv
122- [ 12%] Generating 1_lsu_stbuf .sv
123- [ 18%] Generating 10_lsu_bus_intf .sv
124- [ 25%] Generating 12_beh_lib .sv
125- [ 31%] Generating 13_ifu_mem_ctl .sv
126- [ 37%] Generating 11_ifu_bp_ctl .sv
127- [ 43%] Generating 15_exu .sv
128- [ 50%] Generating 14_mem_lib .sv
121+ [ 6%] Generating 10_lsu_bus_intf .sv
122+ [ 12%] Generating 11_ifu_bp_ctl .sv
123+ [ 18%] Generating 12_beh_lib .sv
124+ [ 25%] Generating 13_ifu_mem_ctl .sv
125+ [ 31%] Generating 14_mem_lib .sv
126+ [ 37%] Generating 15_exu .sv
127+ [ 43%] Generating 16_dec_decode_ctl .sv
128+ [ 50%] Generating 1_lsu_stbuf .sv
129129[ 56%] Generating 2_ahb_to_axi4.sv
130130[ 62%] Generating 3_rvjtag_tap.sv
131- [ 68%] Generating 4_dec_tlu_ctl .sv
132- [ 75%] Generating 5_lsu_bus_buffer .sv
131+ [ 68%] Generating 5_lsu_bus_buffer .sv
132+ [ 75%] Generating 4_dec_tlu_ctl .sv
133133[ 81%] Generating 6_dbg.sv
134134[ 87%] Generating 7_axi4_to_ahb.sv
135135[ 93%] Generating 8_ifu_aln_ctl.sv
0 commit comments