diff --git a/tests/ParameterWithOverriddenWidthInitializedByConst/Makefile.in b/tests/ParameterWithOverriddenWidthInitializedByConst/Makefile.in
new file mode 100644
index 00000000..13dbe44e
--- /dev/null
+++ b/tests/ParameterWithOverriddenWidthInitializedByConst/Makefile.in
@@ -0,0 +1,2 @@
+TOP_FILE := $(TEST_DIR)/top.sv
+TOP_MODULE := top
diff --git a/tests/ParameterWithOverriddenWidthInitializedByConst/main.cpp b/tests/ParameterWithOverriddenWidthInitializedByConst/main.cpp
new file mode 100644
index 00000000..8e0c45f7
--- /dev/null
+++ b/tests/ParameterWithOverriddenWidthInitializedByConst/main.cpp
@@ -0,0 +1,40 @@
+#include <iostream>
+#include <verilated_vcd_c.h>
+
+#define VL_DEBUG
+#include "Vtop.h"
+#include "verilated.h"
+
+static vluint64_t main_time = 0;
+
+double
+sc_time_stamp()
+{
+  return main_time;
+}
+
+int main (int argc, char **argv) {
+  Verilated::commandArgs(argc, argv);
+  Vtop *top = new Vtop();
+
+  Verilated::traceEverOn(true);
+  VerilatedVcdC* tfp = new VerilatedVcdC;
+  top->trace(tfp, 99);
+  tfp->open("dump.vcd");
+
+  while (!Verilated::gotFinish() && (main_time < 100)) {
+    top->eval();
+    tfp->dump(main_time);
+
+    main_time += 1;
+
+    std::cout << "time: " << main_time
+              << " o: " << (int)top->o
+              << std::endl;
+  }
+  top->final();
+  tfp->close();
+  delete top;
+
+  return 0;
+}
diff --git a/tests/ParameterWithOverriddenWidthInitializedByConst/top.sv b/tests/ParameterWithOverriddenWidthInitializedByConst/top.sv
new file mode 100644
index 00000000..324ef5ac
--- /dev/null
+++ b/tests/ParameterWithOverriddenWidthInitializedByConst/top.sv
@@ -0,0 +1,11 @@
+module top(output int o);
+   prim_flop #(
+      .Width(22)
+   ) u_prim_flop(.x(o));
+endmodule
+
+module prim_flop(output int x);
+   parameter int Width = 1;
+   parameter logic [Width-1:0] ResetValue = 15;
+   assign x = int'(ResetValue);
+endmodule
diff --git a/tests/ParameterWithOverriddenWidthInitializedByConst/yosys_script b/tests/ParameterWithOverriddenWidthInitializedByConst/yosys_script
new file mode 100644
index 00000000..ea782476
--- /dev/null
+++ b/tests/ParameterWithOverriddenWidthInitializedByConst/yosys_script
@@ -0,0 +1,6 @@
+plugin -i uhdm
+read_uhdm -debug top.uhdm
+prep -top \top
+write_verilog
+write_verilog yosys.sv
+sim -rstlen 10 -vcd dump.vcd