diff --git a/tests/NestedAssignmentPattern/Makefile.in b/tests/NestedAssignmentPattern/Makefile.in new file mode 100644 index 00000000..13dbe44e --- /dev/null +++ b/tests/NestedAssignmentPattern/Makefile.in @@ -0,0 +1,2 @@ +TOP_FILE := $(TEST_DIR)/top.sv +TOP_MODULE := top diff --git a/tests/NestedAssignmentPattern/main.cpp b/tests/NestedAssignmentPattern/main.cpp new file mode 100644 index 00000000..483ca88e --- /dev/null +++ b/tests/NestedAssignmentPattern/main.cpp @@ -0,0 +1,40 @@ +#include +#include + +#define VL_DEBUG +#include "Vtop.h" +#include "verilated.h" + +static vluint64_t main_time = 0; + +double +sc_time_stamp() +{ + return main_time; +} + +int main (int argc, char **argv) { + Verilated::commandArgs(argc, argv); + Vtop *top = new Vtop(); + + Verilated::traceEverOn(true); + VerilatedVcdC* tfp = new VerilatedVcdC; + top->trace(tfp, 99); + tfp->open("dump.vcd"); + + while (!Verilated::gotFinish() && (main_time < 100)) { + top->eval(); + tfp->dump(main_time); + + main_time += 1; + + std::cout << "time: " << main_time + << " b: " << (top->b?1:0) + << std::endl; + } + top->final(); + tfp->close(); + delete top; + + return 0; +} diff --git a/tests/NestedAssignmentPattern/top.sv b/tests/NestedAssignmentPattern/top.sv new file mode 100644 index 00000000..1a69e24d --- /dev/null +++ b/tests/NestedAssignmentPattern/top.sv @@ -0,0 +1,15 @@ +module top(output [3:0] b); + typedef struct packed { + logic [1:0] addr; + logic sel; + logic rd; + } complex_t; + + parameter complex_t RSP_DEFAULT = '{ + addr: '{default: '1}, + sel: 1'b0, + rd: 1'b1 + }; + assign b = RSP_DEFAULT; + +endmodule diff --git a/tests/NestedAssignmentPattern/yosys_script b/tests/NestedAssignmentPattern/yosys_script new file mode 100644 index 00000000..ea782476 --- /dev/null +++ b/tests/NestedAssignmentPattern/yosys_script @@ -0,0 +1,6 @@ +plugin -i uhdm +read_uhdm -debug top.uhdm +prep -top \top +write_verilog +write_verilog yosys.sv +sim -rstlen 10 -vcd dump.vcd