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olofkolofk
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Add simulation support for SPI Flash
1 parent 207990e commit 9b22a00

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‎sw/Makefile‎

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@@ -1,4 +1,6 @@
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TOOLCHAIN_PREFIX ?= riscv64-unknown-elf-
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RESET_VECTOR ?= 0
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FLASH_ADDR ?= 0x0
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%.elf: %.S
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$(TOOLCHAIN_PREFIX)gcc -nostartfiles -march=rv32i -mabi=ilp32 -Tlink.ld -o$@ $<
@@ -8,5 +10,19 @@ TOOLCHAIN_PREFIX ?= riscv64-unknown-elf-
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$(TOOLCHAIN_PREFIX)objcopy -O binary $< $@
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%.ihex: %.elf
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$(TOOLCHAIN_PREFIX)objcopy -O ihex $< $@
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%.ub: %.bin
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mkimage \
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-A riscv \
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-C none \
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-T standalone \
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-a 0x0 \
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-e $(RESET_VECTOR) \
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-n '$@' \
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-d $< \
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$@
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%.ubvh: %.ub
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objcopy --change-addresses $(FLASH_ADDR) -I binary -O verilog $< $@
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clean:
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rm -f *.elf *.bin *.vh

‎sw/hello.ubvh‎

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@00000000
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27 05 19 56 11 A4 6D 25 5D 53 EE 8A 00 00 00 45
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00 00 00 00 00 00 00 00 6D 43 B1 80 05 1A 01 00
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68 65 6C 6C 6F 2E 75 62 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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37 15 00 80 13 05 85 00 97 05 00 00 93 85 85 02
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83 82 05 00 23 00 55 00 93 85 15 00 83 82 05 00
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E3 9A 02 FE B7 15 00 80 93 85 95 00 23 A0 05 00
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53 77 65 52 56 2B 46 75 73 65 53 6F 43 20 72 6F
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63 6B 73 0A 00

‎sw/spi_uimage_loader.S‎

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/* Assembly program to go into the boot ROM
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For use with the simple_spi core and standard SPI flash
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interface-compatible parts (ST M25P16 for example.)
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Loads an image in the U-boot uimage format from SPI Flash
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in the the RAM at the address specified in the uimage header.
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After loading is completed, it will jump to the entry point
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address specified in the uimage header.
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To keep it simple, only basic sanity checks are made on the image
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*/
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/* Base address of the SPI controller used to communicate with the Flash */
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#ifndef SPI_BASE
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#define SPI_BASE 0x80001040
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#endif
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/* Base address of the SPI controller used to blink LED */
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#ifndef GPIO_BASE
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#define GPIO_BASE 0x80001010
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#endif
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/* 24-bit address in SPI Flash where application image is stored */
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#ifndef BOOTROM_ADDR
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#define BOOTROM_ADDR 0x000000
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#endif
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/* Flash needs 300 us to warm up from power-on. In practice, this is only an
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issue in simulations as FPGA boot is far longer than 300 us
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*/
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#ifndef INIT_DELAY
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#define INIT_DELAY 700
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#endif
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#define RAM_INIT_DONE 0x8000100A
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#define RETRIES 3
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#define SPI_SPCR 0x00
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#define SPI_SPSR 0x08
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#define SPI_SPDR 0x10
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#define SPI_SPER 0x18
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#define SPI_SPSS 0x20
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#define SPI_SPSS_INIT 0x1
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#define SPI_SPSR_RX_CHECK 0x01 /* Check bit 0 is cleared, fifo !empty*/
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.globl _start
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_start:
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/* Registers used
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ra link register
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t1 temp register
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t2 temp register
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s0 Image size
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s1 Load address
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s2 Reset vector
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s3 Retry counter
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gp SPI master base address
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a3 get_rx_data return value
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t3 temp register
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*/
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boot_init:
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#if INIT_DELAY
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li t1, INIT_DELAY
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and t2, zero, zero
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1: addi t2,t2,1
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bne t1, t2, 1b
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#endif
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/* Wait until RAM initialization is done */
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li t1, RAM_INIT_DONE
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1: lbu t2, 0(t1)
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beqz t2, 1b
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/* Load SPI base address to gp */
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li gp, SPI_BASE
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li s3, RETRIES
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spi_init:
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/* Clear slave selects */
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sb zero, SPI_SPSS(gp)
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fence
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/* Set clock divider to 4 (arbitrarily chosen value)
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and enable controller */
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addi t1, zero, 0x40 | 0x01
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sb t1, SPI_SPCR(gp)
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fence
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/* Set appropriate slave select */
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addi t1, zero, 1
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sb t1, SPI_SPSS(gp)
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fence
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/* Set command to READ at BOOTROM_ADDR */
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li a0, ((BOOTROM_ADDR & 0xFF) <<24) | ((BOOTROM_ADDR & 0xFF00) << 8) | ((BOOTROM_ADDR & 0xFF0000) >> 8) | 0x3
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jal spi_xfer
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/* Get magic word */
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jal spi_xfer
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/* Verify that magic word is (endian-swapped) 0x27051956
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Retry a couple of times before we give up */
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addi s3, s3, -1
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beqz s3, boot_fail
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li t1, 0x56190527
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bne t1, a1, spi_init
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read_header:
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/* Dummy read two words */
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jal spi_xfer
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jal spi_xfer
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/* Load image size to s0 */
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jal spi_xfer
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jal endian_swap
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mv s0, a2
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/* Load RAM base address to s1 */
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jal spi_xfer
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jal endian_swap
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mv s1, a2
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/* Load reset vector to s2 */
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jal spi_xfer
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jal endian_swap
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mv s2, a2
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/* Dummy read rest of header */
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jal spi_xfer //dcrc
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jal spi_xfer //os, arch, type, comp
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jal spi_xfer
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jal spi_xfer
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jal spi_xfer
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jal spi_xfer
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jal spi_xfer
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jal spi_xfer
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jal spi_xfer
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jal spi_xfer
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/* Clear number of copied bytes */
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addi s4, zero, 0
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copy_to_ram:
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jal spi_xfer
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/* Set memory store address */
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add t1, s1, s4
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/* Write word to RAM */
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sw a1, 0(t1)
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fence
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/* Increase counter */
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addi s4, s4, 4
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/* Check if file is completely copied */
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bge s0, s4, copy_to_ram
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/* Jump to entry point */
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goto_reset:
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jr s2
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/* Spin here on boot failures */
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boot_fail: j boot_fail
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/* Reads ddccbbaa from a1, stores aabbccdd to a2 */
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endian_swap:
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slli a2, a1, 24 // a2 = aa000000
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srli t1, a1, 8 // t1 = 00ddccbb
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andi t1, t1, 0xff // t1 = 000000bb
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slli t1, t1, 16 // t1 = 00bb0000
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or a2, a2, t1 // a2 = aabb0000
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srli t1, a1, 16 // t1 = 0000ddcc
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andi t1, t1, 0xff // t1 = 000000cc
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slli t1, t1, 8 // t1 = 0000cc00
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or a2, a2, t1 // a2 = aabbcc00
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srli t1, a1, 24 // t1 = 000000dd
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or a2, a2, t1 // a2 = aabbccdd
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ret
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spi_xfer:
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/* Loop four times */
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addi t0, zero, 4
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spi_xfer_loop:
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/* Send data in a0[7:0] */
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sb a0, SPI_SPDR(gp)
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fence
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spi_xfer_poll:
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/* Wait for data in RX FIFO */
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lbu t1, SPI_SPSR(gp)
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fence
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andi t1, t1, SPI_SPSR_RX_CHECK
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bnez t1, spi_xfer_poll
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srli a1, a1, 8
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lbu t1, SPI_SPDR(gp)
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slli t1, t1, 24
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or a1, a1, t1
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srli a0, a0, 8
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addi t0, t0, -1
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bnez t0, spi_xfer_loop
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ret

‎sw/spi_uimage_loader.vh‎

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000073B32BC00313
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FE731EE300138393
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00A3031380001337
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FE038EE300034383
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04018193800011B7
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0201802300300993
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041003130FF0000F
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0FF0000F00618023
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0261802300100313
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003005130FF0000F
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0C0000EF0C4000EF
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08098263FFF98993
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5273031356190337
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0A8000EFFCB312E3
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0A0000EF0A4000EF
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0006041306C000EF
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060000EF094000EF
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088000EF00060493
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00060913054000EF
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078000EF07C000EF
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070000EF074000EF
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068000EF06C000EF
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060000EF064000EF
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058000EF05C000EF
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050000EF00000A13
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00B3202301448333
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004A0A130FF0000F
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00090067FF4456E3
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018596130000006F
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0FF373130085D313
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0066663301031313
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0FF373130105D313
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0066663300831313
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006666330185D313
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0040029300008067
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0FF0000F00A18823
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0FF0000F0081C303
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FE031AE300137313
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0101C3030085D593
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0065E5B301831313
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FFF2829300855513
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00008067FC0298E3
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0000000000000000

‎swervolf.core‎

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@@ -36,6 +36,13 @@ filesets:
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depend : [jtag_vpi]
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verilator_waiver: {files: [data/verilator_waiver.vlt : {file_type : vlt}]}
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spi_tb:
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files:
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- tb/s25fl128s.v
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- tb/swervolf_spi_tb.v
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- sw/hello.ubvh : {file_type : user, copyto : hello.ubvh}
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file_type : verilogSource
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nexys_a7_files:
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files :
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- data/vivado_waiver.tcl : {file_type : tclSource}
@@ -48,6 +55,7 @@ filesets:
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bootrom:
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files :
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- sw/blinky.vh : {file_type : user, copyto : blinky.vh}
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- sw/spi_uimage_loader.vh : {file_type : user, copyto : spi_uimage_loader.vh}
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targets:
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sim:
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verilator_options : [--trace, -Wno-fatal]
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toplevel : swervolf_core_tb
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spi_tb:
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default_tool : modelsim
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filesets :
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- bootrom
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- core
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- bfm
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- spi_tb
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generate : [intercon, swerv_default_config]
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parameters : [SIMPRINT=true, ram_init_file, rom_init_file, flash_init_file, mem_clear=true, timeout, vcd]
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tools:
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modelsim:
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vlog_options :
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- -mfcu
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- -cuautoname=du
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- config/common_defines.vh
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- -timescale 1ns/1ns
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toplevel : swervolf_spi_tb
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nexys_a7:
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default_tool : vivado
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filesets :
@@ -151,6 +178,11 @@ parameters:
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description : Verilog hex file to use as initial bootrom RAM contents
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paramtype : plusarg
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flash_init_file:
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datatype: file
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description : Verilog hex file to use as initial SPI Flash contents
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paramtype : vlogparam
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signature:
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datatype : file
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paramtype : plusarg

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