Add FixedIOModule (#4874)

Author: tmckay-sifive

src/main/scala-2/chisel3/FixedIOModule.scala

@@ -28,6 +28,14 @@ sealed trait FixedIOBaseModule[A <: Data] extends BaseModule {
   */
 class FixedIORawModule[A <: Data](final val ioGenerator: A) extends RawModule with FixedIOBaseModule[A]
 
+/** A Chisel module whose IO (in addition to [[clock]] and [[reset]]) is determined
+ *  by an IO generator. This module cannot have additional IO created by modules that
+ *  extend it.
+  *
+  * @param ioGenerator
+  */
+class FixedIOModule[A <: Data](final val ioGenerator: A) extends Module with FixedIOBaseModule[A]
+
 /** A Chisel blackbox whose IO is determined by an IO generator.  This module
   * cannot have additional IO created by modules that extend it.
   *

src/main/scala-3/chisel3/FixedIOModule.scala

@@ -25,6 +25,14 @@ sealed trait FixedIOBaseModule[A <: Data] extends BaseModule {
   */
 class FixedIORawModule[A <: Data](final val ioGenerator: A) extends RawModule with FixedIOBaseModule[A]
 
+/** A Chisel module whose IO (in addition to [[clock]] and [[reset]]) is determined
+ *  by an IO generator. This module cannot have additional IO created by modules that
+ *  extend it.
+  *
+  * @param ioGenerator
+  */
+class FixedIOModule[A <: Data](final val ioGenerator: A) extends Module with FixedIOBaseModule[A]
+
 /** A Chisel blackbox whose IO is determined by an IO generator.  This module
   * cannot have additional IO created by modules that extend it.
   *

src/test/scala-2/chiselTests/FixedIOModuleSpec.scala

@@ -320,4 +320,20 @@ class FixedIOModuleSpec extends AnyFlatSpec with Matchers with FileCheck {
     ChiselStage.emitCHIRRTL(new Bar) should include("module Foo :")
   }
 
+  "FixedIOModule" should "create a module with flattened IO with clock and reset" in {
+    class Foo(width: Int) extends FixedIOModule[UInt](UInt(width.W)) {
+      override def resetType = Module.ResetType.Synchronous
+      io :<>= DontCare
+    }
+
+    ChiselStage
+      .emitCHIRRTL(new Foo(8))
+      .fileCheck()(
+        """| CHECK: module Foo :
+           | CHECK:   input clock : Clock
+           | CHECK:   input reset : UInt<1>
+           | CHECK:   output io : UInt<8>
+           |""".stripMargin
+      )
+  }
 }