fix up extra waveform dump behavior in svsim (#4592)

When added require statement in ChiselSim/svsim, the delay value will be
set to 0, which will cause an extra dump waveform behavior. So we only
call `eval_step` once to update the design model

Author: Emin017

svsim/src/main/resources/simulation-driver.cpp

@@ -914,6 +914,10 @@ void simulation_main(int argc, char const **argv) {
 }
 
 void run_simulation(int delay) {
+  if(!delay) {
+    testbench->eval_step();
+    return;
+  }
   testbench->eval();
   context->timeInc(delay);
 }