Add --split-verilog to emitSystemVerilogFile (#4867)

Change the behavior of `ChiselStage.emitSystemVerilogFile` to add
`--split-verilog`.  Without this, a user can run into a situation
where (rightly), they get non-Verilog output in the single file output.
Single file output from CIRCT is only intended to be used for testing.

Instead of telling users that they have to add "--split-verilog", just add
it by default with no way to turn it off.  I don't see a reason why a user
_should_ be able to turn this off as the "off" mode is only for testing
and this testing can be just as easily done with `emitSystemVerilog`.

Fixes #3933.

Signed-off-by: Schuyler Eldridge <[email protected]>

Author: seldridge

src/main/scala/circt/stage/ChiselStage.scala

@@ -209,20 +209,20 @@ object ChiselStage {
       .value
   }
 
-  /** Compile a Chisel circuit to SystemVerilog with file output
+  /** Compile a Chisel circuit to multiple SystemVerilog files.
     *
     * @param gen         a call-by-name Chisel module
     * @param args        additional command line arguments to pass to Chisel
     * @param firtoolOpts additional command line options to pass to firtool
-    * @return a string containing the Verilog output
+    * @return the annotations that exist after compilation
     */
   def emitSystemVerilogFile(
     gen:         => RawModule,
     args:        Array[String] = Array.empty,
     firtoolOpts: Array[String] = Array.empty
   ): AnnotationSeq =
     (new circt.stage.ChiselStage).execute(
-      Array("--target", "systemverilog") ++ args,
+      Array("--target", "systemverilog", "--split-verilog") ++ args,
       Seq(ChiselGeneratorAnnotation(() => gen)) ++ firtoolOpts.map(FirtoolOption(_))
     )
 

src/test/scala-2/circtTests/stage/ChiselStageSpec.scala

@@ -3,7 +3,8 @@
 package circtTests.stage
 
 import chisel3.stage.{ChiselGeneratorAnnotation, CircuitSerializationAnnotation}
-import chisel3.experimental.SourceLine
+import chisel3.experimental.{ExtModule, SourceLine}
+import chisel3.util.HasExtModuleInline
 
 import circt.stage.{ChiselStage, FirtoolOption, PreserveAggregate}
 
@@ -68,6 +69,31 @@ object ChiselStageSpec {
     b := qux.b
   }
 
+  class Corge extends ExtModule with HasExtModuleInline {
+    val a = IO(Input(Bool()))
+    val b = IO(Output(Bool()))
+    setInline(
+      "Corge.v",
+      """|module Corge(
+         |  input a,
+         |  output b
+         |);
+         |  assign b = a;
+         |endmodule
+         |""".stripMargin
+    )
+  }
+
+  class Gralp extends RawModule {
+    val a = IO(Input(Bool()))
+    val b = IO(Output(Bool()))
+    val corge = Module(new Corge)
+    corge.a := a
+    val quz = Module(new Quz)
+    quz.a := corge.b
+    b := quz.b
+  }
+
   import firrtl.annotations.NoTargetAnnotation
   import firrtl.options.Unserializable
   case object DummyAnnotation extends NoTargetAnnotation with Unserializable
@@ -591,7 +617,7 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
       val lines = stdout.split("\n")
       // Fuzzy includes aren't ideal but there is ANSI color in these strings that is hard to match
       lines(0) should include(
-        "src/test/scala-2/circtTests/stage/ChiselStageSpec.scala 95:9: Negative shift amounts are illegal (got -1)"
+        "src/test/scala-2/circtTests/stage/ChiselStageSpec.scala 121:9: Negative shift amounts are illegal (got -1)"
       )
       lines(1) should include("    3.U >> -1")
       lines(2) should include("        ^")
@@ -612,7 +638,7 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
       // Fuzzy includes aren't ideal but there is ANSI color in these strings that is hard to match
       lines.size should equal(2)
       lines(0) should include(
-        "src/test/scala-2/circtTests/stage/ChiselStageSpec.scala 95:9: Negative shift amounts are illegal (got -1)"
+        "src/test/scala-2/circtTests/stage/ChiselStageSpec.scala 121:9: Negative shift amounts are illegal (got -1)"
       )
       (lines(1) should not).include("3.U >> -1")
     }
@@ -1157,7 +1183,7 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
 
     }
 
-    it("emitSystemVerilogFile should support custom Chisel args and firtool options") {
+    it("emitSystemVerilogFile should write to multiple files by default") {
       val targetDir = new File("test_run_dir/ChiselStageSpec/generated")
 
       val args: Array[String] = Array(
@@ -1168,19 +1194,14 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
       info(s"output contains a case statement using --lowering-options=disallowPackedArrays")
       ChiselStage
         .emitSystemVerilogFile(
-          new ChiselStageSpec.Bar,
-          args,
-          Array("--lowering-options=disallowPackedArrays")
+          new ChiselStageSpec.Gralp,
+          args
         )
-        .collectFirst { case EmittedVerilogCircuitAnnotation(a) =>
-          a
-        }
-        .get
-        .value should include("case")
 
-      val expectedOutput = new File(targetDir, "Bar.sv")
-      expectedOutput should (exist)
-      info(s"'$expectedOutput' exists")
+      Seq("Corge.v", "Gralp.sv", "Qux.sv", "Qux.sv").map(new File(targetDir, _)).foreach { file =>
+        info(s"'$file' exists")
+        file should (exist)
+      }
     }
 
     it("should emit btor2 to string") {