[firrtl] Drop Circuit from Target/Named (#4862)

Remove the circuit from both `Target` and `Named`.  For the latter, this
means that `CircuitName` is deleted.

Carry this to its logical conclusion.  The only parts that do require a
change:

1. The RenameMap wants to know if a path is renamed to something
"absolute".  It does this check by looking to see if a module name matches
the circuit name.  (Note: this check is incorrect because it assumes that
a circuit has a single root.  However, this has not been the case since
D/I was implemented.)  Work around this by adding a "circuit name"
parameter to the RenameMap so that this check can still be done.  Note:
large code paths within the rename map that are checking for module or
instance path renames should be completely unreachable.  The only user of
the RenameMap at this point in-tree is `DataView` and this is not going to
do renames involving paths.

2. The LayerControl API needs to know what the circuit name is since this
is part of its ABI.  Previously, the circuit name was known because of a,
now deleted, method on `RawModule`.  Change this to use the module name
itself when determining the ABI setting (file name or macro name).  This
should always be correct because the method to generate the ABI setting
because ChiselSim is always given some top module that it wants to
simulate.  This may be problematic for multi-rooted circuits like inline
directed tests.

3. Users of the Trace API do not have a trivial access to the circuit
name, i.e., the top module.  However, if you are a user of this, you
should know what your top name is without relying on the returned
`CompleteTarget`.  See the `TraceSpec` for an example of this.

Signed-off-by: Schuyler Eldridge <[email protected]>

Author: seldridge

core/src/main/scala/chisel3/Module.scala

@@ -692,7 +692,7 @@ package experimental {
       *
       * @note Should not be called until circuit elaboration is complete
       */
-    final def toNamed: ModuleName = ModuleTarget(this.circuitName, this.name).toNamed
+    final def toNamed: ModuleName = ModuleTarget(this.name).toNamed
 
     /** Returns a FIRRTL ModuleTarget that references this object
       *
@@ -703,7 +703,7 @@ package experimental {
         throwException(s"Internal Error! It's not legal to call .toTarget on an InstanceClone. $m")
       case m: experimental.hierarchy.DefinitionClone[_] =>
         throwException(s"Internal Error! It's not legal to call .toTarget on an DefinitionClone. $m")
-      case _ => ModuleTarget(this.circuitName, this.name)
+      case _ => ModuleTarget(this.name)
     }
 
     /** Returns the real target of a Module which may be an [[InstanceTarget]]
@@ -724,7 +724,7 @@ package experimental {
         m._parent.get.getTarget.instOf(instanceName, name)
       // Without this, we get the wrong CircuitName for the Definition
       case m: experimental.hierarchy.DefinitionClone[_] if m._circuit.nonEmpty =>
-        ModuleTarget(this._circuit.get.circuitName, this.name)
+        ModuleTarget(this.name)
       case _ => this.toTarget
     }
 
@@ -813,7 +813,6 @@ package experimental {
       else {
         val thisAbsolute = this.toAbsoluteTarget
         val rootAbsolute = root.get.toAbsoluteTarget
-        if (thisAbsolute.circuit != thisAbsolute.circuit) fail()
         recurse(thisAbsolute, rootAbsolute)
       }
     }

core/src/main/scala/chisel3/internal/Builder.scala

@@ -12,7 +12,7 @@ import chisel3.internal.binding._
 import chisel3.internal.firrtl.ir._
 import chisel3.internal.firrtl.Converter
 import chisel3.internal.naming._
-import _root_.firrtl.annotations.{Annotation, CircuitName, ComponentName, IsMember, ModuleName, Named, ReferenceTarget}
+import _root_.firrtl.annotations.{Annotation, ComponentName, IsMember, ModuleName, Named, ReferenceTarget}
 import _root_.firrtl.annotations.AnnotationUtils.validComponentName
 import _root_.firrtl.{annoSeqToSeq, AnnotationSeq}
 import _root_.firrtl.renamemap.MutableRenameMap
@@ -344,20 +344,6 @@ private[chisel3] trait HasId extends chisel3.InstanceId {
     case Some(p)          => p.name
     case None             => throwException(s"$instanceName doesn't have a parent")
   }
-  def circuitName: String = _parent match {
-    case None =>
-      // Only modules have circuits
-      this match {
-        case b: BaseModule =>
-          b._circuit match {
-            case Some(c) => c.circuitName
-            case None    => instanceName
-          }
-        case _ => instanceName
-      }
-    case Some(ViewParent) => reifyParent.circuitName
-    case Some(p)          => p.circuitName
-  }
 }
 
 /** Holds the implementation of toNamed for Data and MemBase */
@@ -368,7 +354,7 @@ private[chisel3] trait NamedComponent extends HasId {
     */
   final def toNamed: ComponentName = {
     assertValidTarget()
-    ComponentName(this.instanceName, ModuleName(this.parentModName, CircuitName(this.circuitName)))
+    ComponentName(this.instanceName, ModuleName(this.parentModName))
   }
 
   /** Returns a FIRRTL ReferenceTarget that references this object
@@ -953,8 +939,8 @@ private[chisel3] object Builder extends LazyLogging {
   // Builds a RenameMap for all Views that do not correspond to a single Data
   // These Data give a fake ReferenceTarget for .toTarget and .toReferenceTarget that the returned
   // RenameMap can split into the constituent parts
-  private[chisel3] def makeViewRenameMap: MutableRenameMap = {
-    val renames = MutableRenameMap()
+  private[chisel3] def makeViewRenameMap(circuitName: String): MutableRenameMap = {
+    val renames = MutableRenameMap(circuitName)
     for (view <- unnamedViews if !view.isLit) { // Aggregates can be literals too!
       reifySingleTarget(view) match {
         // If the target reifies to a single target, we don't need to rename.
@@ -1131,7 +1117,7 @@ private[chisel3] object Builder extends LazyLogging {
           components.last.name,
           components.toSeq,
           annotations.toSeq,
-          makeViewRenameMap,
+          makeViewRenameMap(circuitName = components.last.name),
           typeAliases,
           layerAdjacencyList(layer.Layer.Root).map(foldLayers).toSeq,
           optionDefs

core/src/main/scala/chisel3/internal/package.scala

@@ -109,7 +109,7 @@ package object internal {
     // the Converter
     // Note that this is not overriding .toAbsoluteTarget, that is a final def in BaseModule that delegates
     // to this method
-    private[chisel3] val absoluteTarget: IsModule = ModuleTarget(this.circuitName, "_$$AbsoluteView$$_")
+    private[chisel3] val absoluteTarget: IsModule = ModuleTarget("_$$AbsoluteView$$_")
 
     // This module is not instantiable
     override private[chisel3] def generateComponent():  Option[Component] = None