@@ -377,6 +377,35 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with
377377 log should include(" Can only bore into modules that are not fully closed" )
378378 }
379379
380+ it should " support boring on a Module even after .toInstance (and accessing a port)" in {
381+ import chisel3 .experimental .hierarchy ._
382+ @ instantiable
383+ class Bar extends RawModule {
384+ @ public val port = IO (Output (UInt (8 .W )))
385+ val a_wire = WireInit (UInt (1 .W ), DontCare )
386+ }
387+ class Foo extends RawModule {
388+ val bar = Module (new Bar )
389+ val bi = bar.toInstance
390+ val x = BoringUtils .bore(bar.a_wire)
391+ val p = bi.port // Previously, the lookup here would close the module due to reflecting on the IOs of bar
392+ val y = BoringUtils .bore(bar.a_wire)
393+ }
394+
395+ generateFirrtlAndFileCheck(new Foo )(
396+ """ |CHECK-LABEL: module Bar :
397+ |CHECK: output port : UInt<8>
398+ |CHECK: output x_bore : UInt<1>
399+ |CHECK: output y_bore : UInt<1>
400+ |CHECK: connect x_bore, a_wire
401+ |CHECK: connect y_bore, a_wire
402+ |CHECK-LABEL: module Foo :
403+ |CHECK: connect x, bar.x_bore
404+ |CHECK: connect y, bar.y_bore
405+ |""" .stripMargin
406+ )
407+ }
408+
380409 it should " not create a new port when source is a port" in {
381410 class Baz extends RawModule {
382411 val a = IO (Output (Bool ()))
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