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tmckay-sifivetmckay-sifive
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Fix potential name collision caused by LTL properties (#4551)
1 parent b5384d9 commit 5871a65

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2 files changed

+90
-62
lines changed

2 files changed

+90
-62
lines changed

‎src/main/scala-2/chisel3/util/circt/LTLIntrinsics.scala‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ private[chisel3] object UnaryLTLIntrinsic {
3737
)(
3838
implicit sourceInfo: SourceInfo
3939
): Bool =
40-
BaseIntrinsic(f"ltl_$intrinsicName", Bool(), params)(_in).suggestName(intrinsicName)
40+
BaseIntrinsic(f"ltl_$intrinsicName", Bool(), params)(_in).suggestName(f"ltl_$intrinsicName")
4141
}
4242

4343
/** Base instrinsic for all binary intrinsics with `lhs`, `rhs`, and `out` ports. */
@@ -50,7 +50,7 @@ private[chisel3] object BinaryLTLIntrinsic {
5050
)(
5151
implicit sourceInfo: SourceInfo
5252
): Bool =
53-
BaseIntrinsic(f"ltl_$intrinsicName", Bool(), params)(lhs, rhs).suggestName(intrinsicName)
53+
BaseIntrinsic(f"ltl_$intrinsicName", Bool(), params)(lhs, rhs).suggestName(f"ltl_$intrinsicName")
5454
}
5555

5656
/** A wrapper intrinsic for the CIRCT `ltl.and` operation. */

‎src/test/scala/chiselTests/LTLSpec.scala‎

Lines changed: 88 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -49,15 +49,21 @@ class LTLSpec extends AnyFlatSpec with Matchers with ChiselRunners {
4949
chirrtl should include("input a : UInt<1>")
5050
chirrtl should include("input b : UInt<1>")
5151
chirrtl should include("input c : UInt<1>")
52-
chirrtl should include(f"node delay = intrinsic(circt_ltl_delay<delay = 1, length = 0> : UInt<1>, a) $sourceLoc")
53-
chirrtl should include(f"node delay_1 = intrinsic(circt_ltl_delay<delay = 2, length = 2> : UInt<1>, b) $sourceLoc")
54-
chirrtl should include(f"node delay_2 = intrinsic(circt_ltl_delay<delay = 5> : UInt<1>, c) $sourceLoc")
55-
chirrtl should include(f"node delay_3 = intrinsic(circt_ltl_delay<delay = 1, length = 0> : UInt<1>, b) $sourceLoc")
56-
chirrtl should include(f"node concat = intrinsic(circt_ltl_concat : UInt<1>, a, delay_3) $sourceLoc")
57-
chirrtl should include(f"node delay_4 = intrinsic(circt_ltl_delay<delay = 0> : UInt<1>, b) $sourceLoc")
58-
chirrtl should include(f"node concat_1 = intrinsic(circt_ltl_concat : UInt<1>, a, delay_4) $sourceLoc")
59-
chirrtl should include(f"node delay_5 = intrinsic(circt_ltl_delay<delay = 1> : UInt<1>, b) $sourceLoc")
60-
chirrtl should include(f"node concat_2 = intrinsic(circt_ltl_concat : UInt<1>, a, delay_5) $sourceLoc")
52+
chirrtl should include(
53+
f"node ltl_delay = intrinsic(circt_ltl_delay<delay = 1, length = 0> : UInt<1>, a) $sourceLoc"
54+
)
55+
chirrtl should include(
56+
f"node ltl_delay_1 = intrinsic(circt_ltl_delay<delay = 2, length = 2> : UInt<1>, b) $sourceLoc"
57+
)
58+
chirrtl should include(f"node ltl_delay_2 = intrinsic(circt_ltl_delay<delay = 5> : UInt<1>, c) $sourceLoc")
59+
chirrtl should include(
60+
f"node ltl_delay_3 = intrinsic(circt_ltl_delay<delay = 1, length = 0> : UInt<1>, b) $sourceLoc"
61+
)
62+
chirrtl should include(f"node ltl_concat = intrinsic(circt_ltl_concat : UInt<1>, a, ltl_delay_3) $sourceLoc")
63+
chirrtl should include(f"node ltl_delay_4 = intrinsic(circt_ltl_delay<delay = 0> : UInt<1>, b) $sourceLoc")
64+
chirrtl should include(f"node ltl_concat_1 = intrinsic(circt_ltl_concat : UInt<1>, a, ltl_delay_4) $sourceLoc")
65+
chirrtl should include(f"node ltl_delay_5 = intrinsic(circt_ltl_delay<delay = 1> : UInt<1>, b) $sourceLoc")
66+
chirrtl should include(f"node ltl_concat_2 = intrinsic(circt_ltl_concat : UInt<1>, a, ltl_delay_5) $sourceLoc")
6167
}
6268
it should "compile sequence delay operations" in {
6369
ChiselStage.emitSystemVerilog(new DelaysMod)
@@ -78,8 +84,8 @@ class LTLSpec extends AnyFlatSpec with Matchers with ChiselRunners {
7884
chirrtl should include("input d : UInt<1>")
7985
chirrtl should include("input e : UInt<1>")
8086
chirrtl should include(f"intrinsic(circt_ltl_concat : UInt<1>, a, b) $sourceLoc")
81-
chirrtl should include(f"node concat_1 = intrinsic(circt_ltl_concat : UInt<1>, c, d) $sourceLoc")
82-
chirrtl should include(f"intrinsic(circt_ltl_concat : UInt<1>, concat_1, e) $sourceLoc")
87+
chirrtl should include(f"node ltl_concat_1 = intrinsic(circt_ltl_concat : UInt<1>, c, d) $sourceLoc")
88+
chirrtl should include(f"intrinsic(circt_ltl_concat : UInt<1>, ltl_concat_1, e) $sourceLoc")
8389
}
8490
it should "compile sequence concat operations" in {
8591
ChiselStage.emitSystemVerilog(new ConcatMod)
@@ -102,14 +108,16 @@ class LTLSpec extends AnyFlatSpec with Matchers with ChiselRunners {
102108
chirrtl should include("input c : UInt<1>")
103109
chirrtl should include("input d : UInt<1>")
104110
chirrtl should include("input e : UInt<1>")
105-
chirrtl should include(f"node repeat = intrinsic(circt_ltl_repeat<base = 1, more = 0> : UInt<1>, a) $sourceLoc")
106-
chirrtl should include(f"node repeat_1 = intrinsic(circt_ltl_repeat<base = 2, more = 2> : UInt<1>, b) $sourceLoc")
107-
chirrtl should include(f"node repeat_2 = intrinsic(circt_ltl_repeat<base = 5> : UInt<1>, c) $sourceLoc")
111+
chirrtl should include(f"node ltl_repeat = intrinsic(circt_ltl_repeat<base = 1, more = 0> : UInt<1>, a) $sourceLoc")
112+
chirrtl should include(
113+
f"node ltl_repeat_1 = intrinsic(circt_ltl_repeat<base = 2, more = 2> : UInt<1>, b) $sourceLoc"
114+
)
115+
chirrtl should include(f"node ltl_repeat_2 = intrinsic(circt_ltl_repeat<base = 5> : UInt<1>, c) $sourceLoc")
108116
chirrtl should include(
109-
f"node goto_repeat = intrinsic(circt_ltl_goto_repeat<base = 1, more = 2> : UInt<1>, d) $sourceLoc"
117+
f"node ltl_goto_repeat = intrinsic(circt_ltl_goto_repeat<base = 1, more = 2> : UInt<1>, d) $sourceLoc"
110118
)
111119
chirrtl should include(
112-
f"node non_consecutive_repeat = intrinsic(circt_ltl_non_consecutive_repeat<base = 1, more = 2> : UInt<1>, e) $sourceLoc"
120+
f"node ltl_non_consecutive_repeat = intrinsic(circt_ltl_non_consecutive_repeat<base = 1, more = 2> : UInt<1>, e) $sourceLoc"
113121
)
114122
}
115123
it should "compile sequence repeat operations" in {
@@ -140,28 +148,38 @@ class LTLSpec extends AnyFlatSpec with Matchers with ChiselRunners {
140148
val sourceLoc = "@[Foo.scala 1:2]"
141149

142150
// Sequences
143-
chirrtl should include(f"node delay = intrinsic(circt_ltl_delay<delay = 1, length = 0> : UInt<1>, a) $sourceLoc")
144-
chirrtl should include(f"node and = intrinsic(circt_ltl_and : UInt<1>, delay, b) $sourceLoc")
145-
chirrtl should include(f"node or = intrinsic(circt_ltl_or : UInt<1>, delay, b) $sourceLoc")
146-
chirrtl should include(f"node intersect = intrinsic(circt_ltl_intersect : UInt<1>, delay, b) $sourceLoc")
147-
chirrtl should include(f"node intersect_1 = intrinsic(circt_ltl_intersect : UInt<1>, intersect, and) $sourceLoc")
148-
chirrtl should include(f"node intersect_2 = intrinsic(circt_ltl_intersect : UInt<1>, intersect_1, or) $sourceLoc")
149-
chirrtl should include(f"node clock_1 = intrinsic(circt_ltl_clock : UInt<1>, delay, clock) $sourceLoc")
151+
chirrtl should include(
152+
f"node ltl_delay = intrinsic(circt_ltl_delay<delay = 1, length = 0> : UInt<1>, a) $sourceLoc"
153+
)
154+
chirrtl should include(f"node ltl_and = intrinsic(circt_ltl_and : UInt<1>, ltl_delay, b) $sourceLoc")
155+
chirrtl should include(f"node ltl_or = intrinsic(circt_ltl_or : UInt<1>, ltl_delay, b) $sourceLoc")
156+
chirrtl should include(f"node ltl_intersect = intrinsic(circt_ltl_intersect : UInt<1>, ltl_delay, b) $sourceLoc")
157+
chirrtl should include(
158+
f"node ltl_intersect_1 = intrinsic(circt_ltl_intersect : UInt<1>, ltl_intersect, ltl_and) $sourceLoc"
159+
)
160+
chirrtl should include(
161+
f"node ltl_intersect_2 = intrinsic(circt_ltl_intersect : UInt<1>, ltl_intersect_1, ltl_or) $sourceLoc"
162+
)
163+
chirrtl should include(f"node ltl_clock = intrinsic(circt_ltl_clock : UInt<1>, ltl_delay, clock) $sourceLoc")
150164

151165
// Properties
152-
chirrtl should include(f"node eventually = intrinsic(circt_ltl_eventually : UInt<1>, a) $sourceLoc")
153-
chirrtl should include(f"node and_1 = intrinsic(circt_ltl_and : UInt<1>, eventually, b) $sourceLoc")
154-
chirrtl should include(f"node or_1 = intrinsic(circt_ltl_or : UInt<1>, eventually, b) $sourceLoc")
155-
chirrtl should include(f"node intersect_3 = intrinsic(circt_ltl_intersect : UInt<1>, eventually, b) $sourceLoc")
166+
chirrtl should include(f"node ltl_eventually = intrinsic(circt_ltl_eventually : UInt<1>, a) $sourceLoc")
167+
chirrtl should include(f"node ltl_and_1 = intrinsic(circt_ltl_and : UInt<1>, ltl_eventually, b) $sourceLoc")
168+
chirrtl should include(f"node ltl_or_1 = intrinsic(circt_ltl_or : UInt<1>, ltl_eventually, b) $sourceLoc")
156169
chirrtl should include(
157-
f"node intersect_4 = intrinsic(circt_ltl_intersect : UInt<1>, intersect_3, and_1) $sourceLoc"
170+
f"node ltl_intersect_3 = intrinsic(circt_ltl_intersect : UInt<1>, ltl_eventually, b) $sourceLoc"
158171
)
159-
chirrtl should include(f"node intersect_5 = intrinsic(circt_ltl_intersect : UInt<1>, intersect_4, or_1) $sourceLoc")
160-
chirrtl should include(f"node clock_2 = intrinsic(circt_ltl_clock : UInt<1>, eventually, clock) $sourceLoc")
172+
chirrtl should include(
173+
f"node ltl_intersect_4 = intrinsic(circt_ltl_intersect : UInt<1>, ltl_intersect_3, ltl_and_1) $sourceLoc"
174+
)
175+
chirrtl should include(
176+
f"node ltl_intersect_5 = intrinsic(circt_ltl_intersect : UInt<1>, ltl_intersect_4, ltl_or_1) $sourceLoc"
177+
)
178+
chirrtl should include(f"node ltl_clock_1 = intrinsic(circt_ltl_clock : UInt<1>, ltl_eventually, clock) $sourceLoc")
161179

162180
// Until
163-
chirrtl should include(f"node until = intrinsic(circt_ltl_until : UInt<1>, delay, b) $sourceLoc")
164-
chirrtl should include(f"node until_1 = intrinsic(circt_ltl_until : UInt<1>, eventually, b) $sourceLoc")
181+
chirrtl should include(f"node ltl_until = intrinsic(circt_ltl_until : UInt<1>, ltl_delay, b) $sourceLoc")
182+
chirrtl should include(f"node ltl_until_1 = intrinsic(circt_ltl_until : UInt<1>, ltl_eventually, b) $sourceLoc")
165183
}
166184
it should "compile and, or, intersect, and clock operations" in {
167185
ChiselStage.emitSystemVerilog(new AndOrClockMod)
@@ -199,15 +217,19 @@ class LTLSpec extends AnyFlatSpec with Matchers with ChiselRunners {
199217

200218
// Non-overlapping (emitted as `a ## true |-> b`)
201219
chirrtl should include(
202-
f"node delay = intrinsic(circt_ltl_delay<delay = 1, length = 0> : UInt<1>, UInt<1>(0h1)) $sourceLoc"
220+
f"node ltl_delay = intrinsic(circt_ltl_delay<delay = 1, length = 0> : UInt<1>, UInt<1>(0h1)) $sourceLoc"
221+
)
222+
chirrtl should include(f"node ltl_concat = intrinsic(circt_ltl_concat : UInt<1>, a, ltl_delay) $sourceLoc")
223+
chirrtl should include(
224+
f"node ltl_implication_2 = intrinsic(circt_ltl_implication : UInt<1>, ltl_concat, b) $sourceLoc"
225+
)
226+
chirrtl should include(
227+
f"node ltl_delay_1 = intrinsic(circt_ltl_delay<delay = 1, length = 0> : UInt<1>, UInt<1>(0h1)) $sourceLoc"
203228
)
204-
chirrtl should include(f"node concat = intrinsic(circt_ltl_concat : UInt<1>, a, delay) $sourceLoc")
205-
chirrtl should include(f"node implication_2 = intrinsic(circt_ltl_implication : UInt<1>, concat, b) $sourceLoc")
229+
chirrtl should include(f"node ltl_concat_1 = intrinsic(circt_ltl_concat : UInt<1>, a, ltl_delay_1) $sourceLoc")
206230
chirrtl should include(
207-
f"node delay_1 = intrinsic(circt_ltl_delay<delay = 1, length = 0> : UInt<1>, UInt<1>(0h1)) $sourceLoc"
231+
f"node ltl_implication_3 = intrinsic(circt_ltl_implication : UInt<1>, ltl_concat_1, b) $sourceLoc"
208232
)
209-
chirrtl should include(f"node concat_1 = intrinsic(circt_ltl_concat : UInt<1>, a, delay_1) $sourceLoc")
210-
chirrtl should include(f"node implication_3 = intrinsic(circt_ltl_implication : UInt<1>, concat_1, b) $sourceLoc")
211233
}
212234
it should "compile property implication operation" in {
213235
ChiselStage.emitSystemVerilog(new PropImplicationMod)
@@ -280,9 +302,9 @@ class LTLSpec extends AnyFlatSpec with Matchers with ChiselRunners {
280302
val sourceLoc = "@[Foo.scala 1:2]"
281303
chirrtl should include("node has_been_reset = intrinsic(circt_has_been_reset : UInt<1>, clock, reset)")
282304
chirrtl should include("node disable = eq(has_been_reset, UInt<1>(0h0))")
283-
chirrtl should include(f"node clock_1 = intrinsic(circt_ltl_clock : UInt<1>, a, clock) $sourceLoc")
305+
chirrtl should include(f"node ltl_clock = intrinsic(circt_ltl_clock : UInt<1>, a, clock) $sourceLoc")
284306
chirrtl should include(f"node _T = eq(disable, UInt<1>(0h0)) $sourceLoc")
285-
chirrtl should include(f"intrinsic(circt_verif_$op, clock_1, _T) $sourceLoc")
307+
chirrtl should include(f"intrinsic(circt_verif_$op, ltl_clock, _T) $sourceLoc")
286308
}
287309
}
288310

@@ -311,17 +333,17 @@ class LTLSpec extends AnyFlatSpec with Matchers with ChiselRunners {
311333
AssertProperty(a, clock = Some(c), disable = Some(b.asDisable))
312334
})
313335
// with clock; emitted as `assert(clock(a, c))`
314-
chirrtl should include("node clock = intrinsic(circt_ltl_clock : UInt<1>, a, c)")
315-
chirrtl should include("intrinsic(circt_verif_assert, clock)")
336+
chirrtl should include("node ltl_clock = intrinsic(circt_ltl_clock : UInt<1>, a, c)")
337+
chirrtl should include("intrinsic(circt_verif_assert, ltl_clock)")
316338

317339
// with disable; emitted as `assert(a, disable)`
318340
chirrtl should include("node _T = eq(b, UInt<1>(0h0))")
319341
chirrtl should include("intrinsic(circt_verif_assert, a, _T)")
320342

321343
// with clock and disable; emitted as `assert(clock(disable(a, b), c))`
322-
chirrtl should include("node clock_1 = intrinsic(circt_ltl_clock : UInt<1>, a, c)")
344+
chirrtl should include("node ltl_clock_1 = intrinsic(circt_ltl_clock : UInt<1>, a, c)")
323345
chirrtl should include("node _T_1 = eq(b, UInt<1>(0h0))")
324-
chirrtl should include("intrinsic(circt_verif_assert, clock_1, _T_1)")
346+
chirrtl should include("intrinsic(circt_verif_assert, ltl_clock_1, _T_1)")
325347
}
326348

327349
class SequenceConvMod extends RawModule {
@@ -343,34 +365,40 @@ class LTLSpec extends AnyFlatSpec with Matchers with ChiselRunners {
343365
chirrtl should include(s"intrinsic(circt_verif_assert, a) $sourceLoc")
344366

345367
// a b
346-
chirrtl should include(s"node concat = intrinsic(circt_ltl_concat : UInt<1>, a, b) $sourceLoc")
347-
chirrtl should include(s"intrinsic(circt_verif_assert, concat) $sourceLoc")
368+
chirrtl should include(s"node ltl_concat = intrinsic(circt_ltl_concat : UInt<1>, a, b) $sourceLoc")
369+
chirrtl should include(s"intrinsic(circt_verif_assert, ltl_concat) $sourceLoc")
348370

349371
// Delay() a
350-
chirrtl should include(s"node delay = intrinsic(circt_ltl_delay<delay = 1, length = 0> : UInt<1>, a) $sourceLoc")
351-
chirrtl should include(s"intrinsic(circt_verif_assert, delay) $sourceLoc")
372+
chirrtl should include(
373+
s"node ltl_delay = intrinsic(circt_ltl_delay<delay = 1, length = 0> : UInt<1>, a) $sourceLoc"
374+
)
375+
chirrtl should include(s"intrinsic(circt_verif_assert, ltl_delay) $sourceLoc")
352376

353377
// a Delay() b
354-
chirrtl should include(s"node delay_1 = intrinsic(circt_ltl_delay<delay = 1, length = 0> : UInt<1>, b) $sourceLoc")
355-
chirrtl should include(s"node concat_1 = intrinsic(circt_ltl_concat : UInt<1>, a, delay_1) $sourceLoc")
356-
chirrtl should include(s"intrinsic(circt_verif_assert, concat_1) $sourceLoc")
378+
chirrtl should include(
379+
s"node ltl_delay_1 = intrinsic(circt_ltl_delay<delay = 1, length = 0> : UInt<1>, b) $sourceLoc"
380+
)
381+
chirrtl should include(s"node ltl_concat_1 = intrinsic(circt_ltl_concat : UInt<1>, a, ltl_delay_1) $sourceLoc")
382+
chirrtl should include(s"intrinsic(circt_verif_assert, ltl_concat_1) $sourceLoc")
357383

358384
// a Delay(2) b
359-
chirrtl should include(s"node delay_2 = intrinsic(circt_ltl_delay<delay = 2, length = 0> : UInt<1>, b) $sourceLoc")
360-
chirrtl should include(s"node concat_2 = intrinsic(circt_ltl_concat : UInt<1>, a, delay_2) $sourceLoc")
361-
chirrtl should include(s"intrinsic(circt_verif_assert, concat_2) $sourceLoc")
385+
chirrtl should include(
386+
s"node ltl_delay_2 = intrinsic(circt_ltl_delay<delay = 2, length = 0> : UInt<1>, b) $sourceLoc"
387+
)
388+
chirrtl should include(s"node ltl_concat_2 = intrinsic(circt_ltl_concat : UInt<1>, a, ltl_delay_2) $sourceLoc")
389+
chirrtl should include(s"intrinsic(circt_verif_assert, ltl_concat_2) $sourceLoc")
362390

363391
// a Delay(42, 1337) b
364392
chirrtl should include(
365-
s"node delay_3 = intrinsic(circt_ltl_delay<delay = 42, length = 1295> : UInt<1>, b) $sourceLoc"
393+
s"node ltl_delay_3 = intrinsic(circt_ltl_delay<delay = 42, length = 1295> : UInt<1>, b) $sourceLoc"
366394
)
367-
chirrtl should include(s"node concat_3 = intrinsic(circt_ltl_concat : UInt<1>, a, delay_3) $sourceLoc")
368-
chirrtl should include(s"intrinsic(circt_verif_assert, concat_3) $sourceLoc")
395+
chirrtl should include(s"node ltl_concat_3 = intrinsic(circt_ltl_concat : UInt<1>, a, ltl_delay_3) $sourceLoc")
396+
chirrtl should include(s"intrinsic(circt_verif_assert, ltl_concat_3) $sourceLoc")
369397

370398
// a Delay(9001, None) sb
371-
chirrtl should include(s"node delay_4 = intrinsic(circt_ltl_delay<delay = 9001> : UInt<1>, b) $sourceLoc")
372-
chirrtl should include(s"node concat_4 = intrinsic(circt_ltl_concat : UInt<1>, a, delay_4) $sourceLoc")
373-
chirrtl should include(s"intrinsic(circt_verif_assert, concat_4) $sourceLoc")
399+
chirrtl should include(s"node ltl_delay_4 = intrinsic(circt_ltl_delay<delay = 9001> : UInt<1>, b) $sourceLoc")
400+
chirrtl should include(s"node ltl_concat_4 = intrinsic(circt_ltl_concat : UInt<1>, a, ltl_delay_4) $sourceLoc")
401+
chirrtl should include(s"intrinsic(circt_verif_assert, ltl_concat_4) $sourceLoc")
374402
}
375403
it should "compile Sequence(...) convenience constructor" in {
376404
ChiselStage.emitSystemVerilog(new SequenceConvMod)

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