[chisel3] Add layers to DesignAnnotation

Add a field to the `DesignAnnotation` that stores all layers that were
generated in a run of Chisel.  This is intended to be used by testing APIs
that need to know what layers exist in order to turn them all on or to
error if a user tries to enable a layer that does not exist.

Signed-off-by: Schuyler Eldridge <[email protected]>

Author: seldridge

core/src/main/scala/chisel3/internal/Builder.scala

@@ -1130,7 +1130,7 @@ private[chisel3] object Builder extends LazyLogging {
           case layer.LayerConfig.Inline     => LayerConfig.Inline
           case layer.LayerConfig.Root       => ???
         }
-        Layer(l.sourceInfo, l.name, config, children.map(foldLayers).toSeq)
+        Layer(l.sourceInfo, l.name, config, children.map(foldLayers).toSeq, l)
       }
 
       val optionDefs = groupByIntoSeq(options)(opt => opt.group).map {

core/src/main/scala/chisel3/internal/firrtl/IR.scala

@@ -425,10 +425,11 @@ private[chisel3] object ir {
   }
 
   final case class Layer(
-    sourceInfo: SourceInfo,
-    name:       String,
-    config:     LayerConfig,
-    children:   Seq[Layer])
+    sourceInfo:  SourceInfo,
+    name:        String,
+    config:      LayerConfig,
+    children:    Seq[Layer],
+    chiselLayer: layer.Layer)
 
   class LayerBlock(val sourceInfo: SourceInfo, val layer: chisel3.layer.Layer) extends Command {
     val region = new Block(sourceInfo)

src/main/scala/chisel3/stage/ChiselAnnotations.scala

@@ -392,7 +392,9 @@ object ChiselOutputFileAnnotation extends HasShellOptions {
   * @param design top-level Chisel design
   * @tparam DUT Type of the top-level Chisel design
   */
-case class DesignAnnotation[DUT <: RawModule](design: DUT) extends NoTargetAnnotation with Unserializable
+case class DesignAnnotation[DUT <: RawModule](design: DUT, layers: Seq[chisel3.layer.Layer] = Seq.empty)
+    extends NoTargetAnnotation
+    with Unserializable
 
 /** Use legacy Chisel width behavior.
   *

src/main/scala/chisel3/stage/phases/Elaborate.scala

@@ -6,6 +6,7 @@ import chisel3.Module
 import chisel3.experimental.hierarchy.core.Definition
 import chisel3.internal.ExceptionHelpers.ThrowableHelpers
 import chisel3.internal.{Builder, BuilderContextCache, DynamicContext}
+import chisel3.internal.firrtl.ir
 import chisel3.stage.{
   ChiselCircuitAnnotation,
   ChiselGeneratorAnnotation,
@@ -53,9 +54,16 @@ class Elaborate extends Phase {
             BuilderContextCache.empty,
             chiselOptions.layerMap
           )
-        val (circuit, dut) =
+        val (circuit, dut) = {
           Builder.build(Module(gen()), context)
-        Seq(ChiselCircuitAnnotation(circuit), DesignAnnotation(dut))
+        }
+
+        // Extract the Chisel layers from a circuit via an in-order walk.
+        def walkLayers(layer: ir.Layer, layers: Seq[chisel3.layer.Layer] = Nil): Seq[chisel3.layer.Layer] = {
+          layer.children.foldLeft(layers :+ layer.chiselLayer) { case (acc, x) => walkLayers(x, acc) }
+        }
+
+        Seq(ChiselCircuitAnnotation(circuit), DesignAnnotation(dut, layers = circuit.layers.flatMap(walkLayers(_))))
       } catch {
         /* if any throwable comes back and we're in "stack trace trimming" mode, then print an error and trim the stack trace
          */

src/test/scala/chiselTests/aop/SelectSpec.scala

@@ -193,7 +193,7 @@ class SelectSpec extends ChiselFlatSpec {
     }
     val top = ChiselGeneratorAnnotation(() => {
       new Top()
-    }).elaborate.collectFirst { case DesignAnnotation(design: Top) => design }.get
+    }).elaborate.collectFirst { case DesignAnnotation(design: Top, _) => design }.get
     Select.collectDeep(top) { case x => x } should equal(Seq(top, top.inst0))
     Select.getDeep(top)(x => Seq(x)) should equal(Seq(top, top.inst0))
     Select.instances(top) should equal(Seq(top.inst0))
@@ -220,7 +220,7 @@ class SelectSpec extends ChiselFlatSpec {
     }
     val top = ChiselGeneratorAnnotation(() => {
       new Top()
-    }).elaborate.collectFirst { case DesignAnnotation(design: Top) => design }.get
+    }).elaborate.collectFirst { case DesignAnnotation(design: Top, _) => design }.get
     intercept[Exception] { Select.collectDeep(top) { case x => x } }
     intercept[Exception] { Select.getDeep(top)(x => Seq(x)) }
     intercept[Exception] { Select.instances(top) }

src/test/scala/chiselTests/experimental/TraceSpec.scala

@@ -72,7 +72,7 @@ class TraceSpec extends ChiselFlatSpec with Matchers {
     }
 
     val (testDir, annos) = compile("TraceFromAnnotations", () => new Module1)
-    val dut = annos.collectFirst { case DesignAnnotation(dut) => dut }.get.asInstanceOf[Module1]
+    val dut = annos.collectFirst { case DesignAnnotation(dut: Module1, _) => dut }.get
     // out of Builder.
 
     val oneTarget = finalTarget(annos)(dut.m0.r.a.a).head
@@ -215,7 +215,7 @@ class TraceSpec extends ChiselFlatSpec with Matchers {
     }
 
     val (_, annos) = compile("TraceFromCollideBundle", () => new CollideModule)
-    val dut = annos.collectFirst { case DesignAnnotation(dut) => dut }.get.asInstanceOf[CollideModule]
+    val dut = annos.collectFirst { case DesignAnnotation(dut: CollideModule, _) => dut }.get
 
     val topName = "CollideModule"
 
@@ -259,7 +259,7 @@ class TraceSpec extends ChiselFlatSpec with Matchers {
     }
 
     val (_, annos) = compile("Inline", () => new Module1)
-    val dut = annos.collectFirst { case DesignAnnotation(dut) => dut }.get.asInstanceOf[Module1]
+    val dut = annos.collectFirst { case DesignAnnotation(dut: Module1, _) => dut }.get
 
     val m0_i = finalTarget(annos)(dut.m0.i).head
     m0_i should be(refTarget("Module1", "m0_i"))
@@ -276,7 +276,7 @@ class TraceSpec extends ChiselFlatSpec with Matchers {
     }
 
     val (_, annos) = compile("ConstantProp", () => new Module0)
-    val dut = annos.collectFirst { case DesignAnnotation(dut) => dut }.get.asInstanceOf[Module0]
+    val dut = annos.collectFirst { case DesignAnnotation(dut: Module0, _) => dut }.get
 
     val i0 = finalTarget(annos)(dut.i0).head
     i0 should be(refTarget("Module0", "i0"))
@@ -319,7 +319,7 @@ class TraceSpec extends ChiselFlatSpec with Matchers {
     }
 
     val (_, annos) = compile("NestedModule", () => new M3)
-    val m3 = annos.collectFirst { case DesignAnnotation(dut) => dut }.get.asInstanceOf[M3]
+    val m3 = annos.collectFirst { case DesignAnnotation(dut: M3, _) => dut }.get
 
     val m2_m1_not = finalTarget(annos)(m3.m2.m1.bar).head
     val m2_not = finalTarget(annos)(m3.m2.foo).head
@@ -337,7 +337,7 @@ class TraceSpec extends ChiselFlatSpec with Matchers {
       Seq(a, b).foreach { a => traceName(a); dontTouch(a) }
     }
     val (_, annos) = compile("NestedModule", () => new M)
-    val dut = annos.collectFirst { case DesignAnnotation(dut) => dut }.get.asInstanceOf[M]
+    val dut = annos.collectFirst { case DesignAnnotation(dut: M, _) => dut }.get
     val allTargets = finalTargetMap(annos)
     allTargets(dut.a.toAbsoluteTarget) should be(Seq(refTarget("M", "a")))
     allTargets(dut.b(0).toAbsoluteTarget) should be(Seq(refTarget("M", "b_0")))