remove DefRegInit, change DefReg API with option defination.

Author: sequencer

core/src/main/scala/chisel3/Reg.scala

@@ -42,7 +42,7 @@ object Reg {
     val clock = Node(Builder.forcedClock)
 
     reg.bind(RegBinding(Builder.forcedUserModule, Builder.currentWhen()))
-    pushCommand(DefReg(sourceInfo, reg, clock))
+    pushCommand(DefReg(sourceInfo, reg, clock, None, None))
     reg
   }
 
@@ -176,7 +176,7 @@ object RegInit {
 
     reg.bind(RegBinding(Builder.forcedUserModule, Builder.currentWhen()))
     requireIsHardware(init, "reg initializer")
-    pushCommand(DefRegInit(sourceInfo, reg, clock.ref, reset.ref, init.ref))
+    pushCommand(DefReg(sourceInfo, reg, clock.ref, Some(reset.ref), Some(init.ref)))
     reg
   }
 

core/src/main/scala/chisel3/internal/firrtl/Converter.scala

@@ -106,12 +106,10 @@ private[chisel3] object Converter {
       Some(fir.DefNode(convert(e.sourceInfo), e.name, expr))
     case e @ DefWire(info, id) =>
       Some(fir.DefWire(convert(info), e.name, extractType(id, info)))
-    case e @ DefReg(info, id, clock) =>
+    case e @ DefReg(info, id, clock, reset, init) =>
       Some(fir.DefRegister(convert(info), e.name, extractType(id, info), convert(clock, ctx, info),
-                           firrtl.Utils.zero, convert(getRef(id, info), ctx, info)))
-    case e @ DefRegInit(info, id, clock, reset, init) =>
-      Some(fir.DefRegister(convert(info), e.name, extractType(id, info), convert(clock, ctx, info),
-                           convert(reset, ctx, info), convert(init, ctx, info)))
+        reset.map(r => convert(r, ctx, info)).getOrElse(firrtl.Utils.zero),
+        init.map(i => convert(i, ctx, info)).getOrElse(convert(getRef(id, info), ctx, info))))
     case e @ DefMemory(info, id, t, size) =>
       Some(firrtl.CDefMemory(convert(info), e.name, extractType(t, info), size, false))
     case e @ DefSeqMemory(info, id, t, size, ruw) =>

core/src/main/scala/chisel3/internal/firrtl/IR.scala

@@ -743,8 +743,7 @@ abstract class Definition extends Command {
 case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition
 case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command
 case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition
-case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition
-case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition
+case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Option[Arg], init: Option[Arg]) extends Definition
 case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition
 case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition
 case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition