add 'enable' field to ir.Printf

Author: tmckay-sifive

core/src/main/scala-2/chisel3/PrintfMacros.scala

@@ -77,7 +77,7 @@ object PrintfMacrosCompat {
     Printable.checkScope(pable)
 
     layer.block(layers.Verification, skipIfAlreadyInBlock = true, skipIfLayersEnabled = true) {
-      pushCommand(chisel3.internal.firrtl.ir.Printf(printfId, sourceInfo, clock.ref, pable))
+      pushCommand(chisel3.internal.firrtl.ir.Printf(printfId, sourceInfo, clock.ref, (!Module.disable.value).ref, pable))
     }
     printfId
   }

core/src/main/scala/chisel3/internal/firrtl/Converter.scala

@@ -190,14 +190,14 @@ private[chisel3] object Converter {
       fir.DefObject(convert(info), e.name, className)
     case e @ Stop(_, info, clock, ret) =>
       fir.Stop(convert(info), ret, convert(clock, ctx, info), firrtl.Utils.one, e.name)
-    case e @ Printf(_, info, clock, pable) =>
+    case e @ Printf(_, info, clock, enable, pable) =>
       val (fmt, args) = unpack(pable, ctx)
       fir.Print(
         convert(info),
         fir.StringLit(fmt),
         args.map(a => convert(a, ctx, info)),
         convert(clock, ctx, info),
-        firrtl.Utils.one,
+        convert(enable, ctx, info),
         e.name
       )
     case e @ ProbeDefine(sourceInfo, sink, probeExpr) =>

core/src/main/scala/chisel3/internal/firrtl/IR.scala

@@ -448,7 +448,7 @@ private[chisel3] object ir {
 
   case class Port(id: Data, dir: SpecifiedDirection, sourceInfo: SourceInfo)
 
-  case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition
+  case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, enable: Arg, pable: Printable) extends Definition
 
   case class ProbeDefine(sourceInfo: SourceInfo, sink: Arg, probe: Arg) extends Command
   case class ProbeForceInitial(sourceInfo: SourceInfo, probe: Arg, value: Arg) extends Command

src/main/scala-2/chisel3/aop/Select.scala

@@ -471,7 +471,7 @@ object Select {
       module,
       (cmd: Command, preds: Seq[Predicate]) => {
         cmd match {
-          case chisel3.internal.firrtl.ir.Printf(id, _, clock, pable) =>
+          case chisel3.internal.firrtl.ir.Printf(id, _, clock, enable, pable) =>
             printfs += Printf(id, preds, pable, getId(clock).asInstanceOf[Clock])
           case other =>
         }