Add option to suppress emission of source locators (#5053)

Author: jackkoenig

core/src/main/scala/chisel3/experimental/hierarchy/core/Definition.scala

@@ -120,7 +120,8 @@ object Definition extends SourceInfoDoc {
         context.definitions,
         context.contextCache,
         context.layerMap,
-        context.inlineTestIncluder
+        context.inlineTestIncluder,
+        context.suppressSourceInfo
       )
     }
     dynamicContext.inDefinition = true

core/src/main/scala/chisel3/internal/Builder.scala

@@ -476,7 +476,8 @@ private[chisel3] class DynamicContext(
   val definitions:        ArrayBuffer[Definition[_]],
   val contextCache:       BuilderContextCache,
   val layerMap:           Map[layer.Layer, layer.Layer],
-  val inlineTestIncluder: InlineTestIncluder
+  val inlineTestIncluder: InlineTestIncluder,
+  val suppressSourceInfo: Boolean
 ) {
   val importedDefinitionAnnos = annotationSeq.collect { case a: ImportDefinitionAnnotation[_] => a }
 
@@ -1122,7 +1123,8 @@ private[chisel3] object Builder extends LazyLogging {
           makeViewRenameMap(circuitName = components.last.name),
           typeAliases,
           layerAdjacencyList(layer.Layer.Root).map(foldLayers).toSeq,
-          optionDefs
+          optionDefs,
+          dynamicContext.suppressSourceInfo
         )
       (ElaboratedCircuit(circuit, dynamicContext.annotationSeq.toSeq), mod)
     }

core/src/main/scala/chisel3/internal/firrtl/IR.scala

@@ -600,13 +600,14 @@ private[chisel3] object ir {
   case class DefClass(id: Class, name: String, ports: Seq[Port], block: Block) extends Component
 
   case class Circuit(
-    name:        String,
-    components:  Seq[Component],
-    annotations: Seq[() => Seq[Annotation]],
-    renames:     RenameMap,
-    typeAliases: Seq[DefTypeAlias],
-    layers:      Seq[Layer],
-    options:     Seq[DefOption]
+    name:               String,
+    components:         Seq[Component],
+    annotations:        Seq[() => Seq[Annotation]],
+    renames:            RenameMap,
+    typeAliases:        Seq[DefTypeAlias],
+    layers:             Seq[Layer],
+    options:            Seq[DefOption],
+    suppressSourceInfo: Boolean
   ) {
     def firrtlAnnotations: Iterable[Annotation] = annotations.flatMap(_().flatMap(_.update(renames)))
   }

core/src/main/scala/chisel3/internal/firrtl/Serializer.scala

@@ -56,11 +56,12 @@ private[chisel3] object Serializer {
 
   // TODO use makeMessage to get ':' filename col separator instead of space
   // Can we optimize the escaping?
-  private def serialize(info: SourceInfo)(implicit b: StringBuilder): Unit = info match {
-    case _:  NoSourceInfo => ()
-    case sl: SourceLine =>
-      b ++= " @["; b ++= fir.FileInfo.fromUnescaped(sl.serialize).escaped; b ++= "]"
-  }
+  private def serialize(info: SourceInfo)(implicit b: StringBuilder, suppressSourceInfo: Boolean): Unit =
+    info match {
+      case sl: SourceLine if !suppressSourceInfo =>
+        b ++= " @["; b ++= fir.FileInfo.fromUnescaped(sl.serialize).escaped; b ++= "]"
+      case _ => ()
+    }
 
   private def reportInternalError(msg: String): Nothing = {
     val link = "https://github.com/chipsalliance/chisel/issues/new"
@@ -164,7 +165,7 @@ private[chisel3] object Serializer {
     args:        Seq[Arg],
     params:      Seq[(String, Param)],
     typeAliases: Seq[String]
-  )(implicit b: StringBuilder): Unit = {
+  )(implicit b: StringBuilder, suppressSourceInfo: Boolean): Unit = {
     if (name.nonEmpty) {
       b ++= "node "; b ++= legalize(name.get); b ++= " = "
     }
@@ -192,8 +193,9 @@ private[chisel3] object Serializer {
 
   /** Serialize Commands */
   private def serializeSimpleCommand(cmd: Command, ctx: Component, typeAliases: Seq[String])(
-    implicit b: StringBuilder,
-    indent:     Int
+    implicit b:         StringBuilder,
+    indent:             Int,
+    suppressSourceInfo: Boolean
   ): Unit = cmd match {
     case e: DefPrim[_] =>
       b ++= "node "; b ++= legalize(e.name); b ++= " = ";
@@ -321,8 +323,9 @@ private[chisel3] object Serializer {
   }
 
   private def serializeCommand(cmd: Command, ctx: Component, typeAliases: Seq[String])(
-    implicit indent: Int
-  ): Iterator[String] =
+    implicit indent:    Int,
+    suppressSourceInfo: Boolean
+  ): Iterator[String] = {
     cmd match {
       case When(info, pred, ifRegion, elseRegion) =>
         val start = {
@@ -338,13 +341,15 @@ private[chisel3] object Serializer {
             newLineNoIndent()
             Iterator(b.toString)
           } else {
-            ifRegion.flatMap(serializeCommand(_, ctx, typeAliases)(indent + 1))
+            ifRegion.flatMap(serializeCommand(_, ctx, typeAliases)(indent + 1, suppressSourceInfo))
           }
         val end = if (elseRegion.nonEmpty) {
           implicit val b = new StringBuilder
           doIndent(); b ++= "else :"
           newLineNoIndent()
-          Iterator(b.toString) ++ elseRegion.flatMap(serializeCommand(_, ctx, typeAliases)(indent + 1))
+          Iterator(b.toString) ++ elseRegion.flatMap(
+            serializeCommand(_, ctx, typeAliases)(indent + 1, suppressSourceInfo)
+          )
         } else Iterator.empty
         start ++ middle ++ end
       case LayerBlock(info, layer, region) =>
@@ -354,15 +359,15 @@ private[chisel3] object Serializer {
           newLineNoIndent()
           Iterator(b.toString)
         }
-        start ++ region.iterator.flatMap(serializeCommand(_, ctx, typeAliases)(indent + 1))
+        start ++ region.iterator.flatMap(serializeCommand(_, ctx, typeAliases)(indent + 1, suppressSourceInfo))
       case Placeholder(_, block) =>
         if (block.isEmpty) {
           implicit val b = new StringBuilder
           doIndent(); b ++= "skip"
           newLineNoIndent()
           Iterator(b.toString)
         } else {
-          block.iterator.flatMap(serializeCommand(_, ctx, typeAliases))
+          block.iterator.flatMap(serializeCommand(_, ctx, typeAliases)(indent, suppressSourceInfo))
         }
       case cmd @ DefContract(info, names, exprs) =>
         val start = {
@@ -382,7 +387,9 @@ private[chisel3] object Serializer {
           newLineNoIndent()
           Iterator(b.toString)
         }
-        start ++ cmd.region.getAllCommands().flatMap(serializeCommand(_, ctx, typeAliases)(indent + 1))
+        start ++ cmd.region
+          .getAllCommands()
+          .flatMap(serializeCommand(_, ctx, typeAliases)(indent + 1, suppressSourceInfo))
       // TODO can we avoid checking 4 less common Commands every single time?
       case simple =>
         // TODO avoid Iterator boxing for every simple command
@@ -392,6 +399,7 @@ private[chisel3] object Serializer {
         newLineNoIndent()
         Iterator(b.toString)
     }
+  }
 
   /** Serialize Chisel IR Block into FIRRTL Statements
     *
@@ -403,7 +411,8 @@ private[chisel3] object Serializer {
     * @return Iterator[String] of the equivalent FIRRTL text
     */
   private def serialize(block: Block, ctx: Component, typeAliases: Seq[String])(
-    implicit indent: Int
+    implicit indent:    Int,
+    suppressSourceInfo: Boolean
   ): Iterator[String] = {
     val commands = block.getCommands()
     val secretCommands = block.getSecretCommands()
@@ -414,7 +423,7 @@ private[chisel3] object Serializer {
       return Iterator(b.toString)
     } else {
       Iterator.empty[String] ++ (commands.iterator ++ secretCommands).flatMap(c =>
-        serializeCommand(c, ctx, typeAliases)
+        serializeCommand(c, ctx, typeAliases)(indent, suppressSourceInfo)
       )
     }
   }
@@ -547,7 +556,7 @@ private[chisel3] object Serializer {
     port:        Port,
     typeAliases: Seq[String],
     topDir:      SpecifiedDirection = SpecifiedDirection.Unspecified
-  )(implicit b: StringBuilder, indent: Int): Unit = {
+  )(implicit b: StringBuilder, indent: Int, suppressSourceInfo: Boolean): Unit = {
     val resolvedDir = SpecifiedDirection.fromParent(topDir, firrtlUserDirOf(port.id))
     val dir = resolvedDir match {
       case SpecifiedDirection.Unspecified | SpecifiedDirection.Output => "output"
@@ -565,7 +574,10 @@ private[chisel3] object Serializer {
   }
 
   // TODO what is typeAliases for? Should it be a Set?
-  private def serialize(component: Component, typeAliases: Seq[String])(implicit indent: Int): Iterator[String] =
+  private def serialize(component: Component, typeAliases: Seq[String])(
+    implicit indent:    Int,
+    suppressSourceInfo: Boolean
+  ): Iterator[String] = {
     component match {
       case ctx @ DefModule(id, name, public, layers, ports, block) =>
         val start = {
@@ -581,7 +593,7 @@ private[chisel3] object Serializer {
           newLineNoIndent() // newline for body, serialize(body) will indent
           b.toString
         }
-        Iterator(start) ++ serialize(block, ctx, typeAliases)(indent + 1)
+        Iterator(start) ++ serialize(block, ctx, typeAliases)(indent + 1, suppressSourceInfo)
 
       case ctx @ DefBlackBox(id, name, ports, topDir, params, knownLayers) =>
         implicit val b = new StringBuilder
@@ -616,7 +628,7 @@ private[chisel3] object Serializer {
           newLineNoIndent() // newline for body, serialize(body) will indent
           b.toString
         }
-        Iterator(start) ++ serialize(block, ctx, typeAliases)(indent + 1)
+        Iterator(start) ++ serialize(block, ctx, typeAliases)(indent + 1, suppressSourceInfo)
 
       case ctx @ DefFormalTest(name, module, params, sourceInfo) =>
         implicit val b = new StringBuilder
@@ -627,8 +639,9 @@ private[chisel3] object Serializer {
         }
         Iterator(b.toString)
     }
+  }
 
-  private def serialize(layer: Layer)(implicit b: StringBuilder, indent: Int): Unit = {
+  private def serialize(layer: Layer)(implicit b: StringBuilder, indent: Int, suppressSourceInfo: Boolean): Unit = {
     newLineAndIndent()
     b ++= "layer "
     b ++= layer.name
@@ -647,13 +660,13 @@ private[chisel3] object Serializer {
     }
     b ++= " :"
     serialize(layer.sourceInfo)
-    layer.children.foreach(serialize(_)(b, indent + 1))
+    layer.children.foreach(serialize(_)(b, indent + 1, suppressSourceInfo))
   }
 
-  private def serialize(layers: Seq[Layer])(implicit indent: Int): Iterator[String] = {
+  private def serialize(layers: Seq[Layer])(implicit indent: Int, suppressSourceInfo: Boolean): Iterator[String] = {
     if (layers.nonEmpty) {
       implicit val b = new StringBuilder
-      layers.foreach(serialize)
+      layers.foreach(serialize(_)(b, indent, suppressSourceInfo))
       newLineNoIndent()
       Iterator(b.toString)
     } else Iterator.empty
@@ -667,7 +680,8 @@ private[chisel3] object Serializer {
 
   // TODO make Annotation serialization lazy
   private def serialize(circuit: Circuit, annotations: Seq[Annotation]): Iterator[String] = {
-    implicit val indent: Int = 0
+    implicit val indent:             Int = 0
+    implicit val suppressSourceInfo: Boolean = circuit.suppressSourceInfo
     val prelude = {
       implicit val b = new StringBuilder
       b ++= s"FIRRTL version $version\n"
@@ -698,7 +712,7 @@ private[chisel3] object Serializer {
       b += NewLine
       Iterator(b.toString)
     } else Iterator.empty
-    val layers = serialize(circuit.layers)(indent + 1)
+    val layers = serialize(circuit.layers)(indent + 1, suppressSourceInfo)
     // TODO what is typeAliases for? Should it be a Set?
     val typeAliasesSeq: Seq[String] = circuit.typeAliases.map(_.name)
     prelude ++
@@ -707,7 +721,7 @@ private[chisel3] object Serializer {
       layers ++
       circuit.components.iterator.zipWithIndex.flatMap { case (m, i) =>
         val newline = Iterator(if (i == 0) s"$NewLine" else s"${NewLine}${NewLine}")
-        newline ++ serialize(m, typeAliasesSeq)(indent + 1)
+        newline ++ serialize(m, typeAliasesSeq)(indent + 1, suppressSourceInfo)
       } ++
       Iterator(s"$NewLine")
   }

release.mill

@@ -7,7 +7,7 @@ import mill.scalalib._
 import mill.scalalib.scalafmt._
 import mill.scalalib.publish._
 import mill.util.Jvm.createJar
-import com.github.lolgab.mill.mima.Mima
+import com.github.lolgab.mill.mima._
 
 //import de.tobiasroeser.mill.vcs.version.VcsVersion
 
@@ -48,6 +48,12 @@ trait Unipublish extends ScalaModule with ChiselPublishModule with Mima {
     os.read.lines(BuildCtx.workspaceRoot / "etc" / "previous-versions.txt")
   }
 
+  override def mimaBinaryIssueFilters = super.mimaBinaryIssueFilters() ++ Seq(
+    // chisel3.internal.firrtl.ir is package private
+    ProblemFilter.exclude[DirectMissingMethodProblem]("chisel3.internal.firrtl.ir*"),
+    ProblemFilter.exclude[MissingTypesProblem]("chisel3.internal.firrtl.ir*")
+  )
+
   /** Publish both this project and the plugin (for the default Scala version) */
   override def publishLocal(
     localMvnRepo: String = null,

src/main/scala/chisel3/stage/ChiselAnnotations.scala

@@ -612,3 +612,26 @@ case object IncludeInlineTestsWithName extends HasShellOptions {
     )
   )
 }
+
+/** Suppress emission of source info in FIRRTL output.
+  *
+  * Use as CLI option `--no-source-info`.
+  *
+  * When this option is enabled, source info (e.g., @[MyFile.scala 42:10]) will not be
+  * emitted in the generated FIRRTL output. This can be useful for reducing output size or
+  * for generating more stable output.
+  */
+case object SuppressSourceInfoAnnotation
+    extends NoTargetAnnotation
+    with ChiselOption
+    with HasShellOptions
+    with Unserializable {
+
+  val options = Seq(
+    new ShellOption[Unit](
+      longOption = "no-source-info",
+      toAnnotationSeq = _ => Seq(SuppressSourceInfoAnnotation),
+      helpText = "Suppress emission of source info in FIRRTL output"
+    )
+  )
+}

src/main/scala/chisel3/stage/ChiselOptions.scala

@@ -19,7 +19,8 @@ class ChiselOptions private[stage] (
   val includeUtilMetadata: Boolean = false,
   val useSRAMBlackbox:     Boolean = false,
   val elaboratedCircuit:   Option[ElaboratedCircuit] = None,
-  val inlineTestIncluder:  InlineTestIncluder = InlineTestIncluder.none
+  val inlineTestIncluder:  InlineTestIncluder = InlineTestIncluder.none,
+  val suppressSourceInfo:  Boolean = false
 ) {
 
   private[stage] def copy(
@@ -33,7 +34,8 @@ class ChiselOptions private[stage] (
     includeUtilMetadata: Boolean = includeUtilMetadata,
     useSRAMBlackbox:     Boolean = useSRAMBlackbox,
     elaboratedCircuit:   Option[ElaboratedCircuit] = elaboratedCircuit,
-    inlineTestIncluder:  InlineTestIncluder = inlineTestIncluder
+    inlineTestIncluder:  InlineTestIncluder = inlineTestIncluder,
+    suppressSourceInfo:  Boolean = suppressSourceInfo
   ): ChiselOptions = {
 
     new ChiselOptions(
@@ -47,7 +49,8 @@ class ChiselOptions private[stage] (
       includeUtilMetadata = includeUtilMetadata,
       useSRAMBlackbox = useSRAMBlackbox,
       elaboratedCircuit = elaboratedCircuit,
-      inlineTestIncluder = inlineTestIncluder
+      inlineTestIncluder = inlineTestIncluder,
+      suppressSourceInfo = suppressSourceInfo
     )
 
   }

src/main/scala/chisel3/stage/package.scala

@@ -38,6 +38,7 @@ package object stage {
             c.copy(inlineTestIncluder = c.inlineTestIncluder.includeModule(glob))
           case IncludeInlineTestsWithNameAnnotation(glob) =>
             c.copy(inlineTestIncluder = c.inlineTestIncluder.includeTest(glob))
+          case SuppressSourceInfoAnnotation => c.copy(suppressSourceInfo = true)
         }
       }
 

src/main/scala/chisel3/stage/phases/Elaborate.scala

@@ -54,7 +54,8 @@ class Elaborate extends Phase {
             ArrayBuffer[Definition[_]](),
             BuilderContextCache.empty,
             chiselOptions.layerMap,
-            chiselOptions.inlineTestIncluder
+            chiselOptions.inlineTestIncluder,
+            chiselOptions.suppressSourceInfo
           )
         val (elaboratedCircuit, dut) = {
           Builder.build(Module(gen()), context)

src/main/scala/circt/stage/Shell.scala

@@ -13,6 +13,7 @@ import chisel3.stage.{
   PrintFullStackTraceAnnotation,
   RemapLayer,
   SourceRootAnnotation,
+  SuppressSourceInfoAnnotation,
   ThrowOnFirstErrorAnnotation,
   UseLegacyWidthBehavior,
   UseSRAMBlackbox,
@@ -54,7 +55,8 @@ trait CLI extends BareShell { this: BareShell =>
     IncludeUtilMetadata,
     UseSRAMBlackbox,
     IncludeInlineTestsForModule,
-    IncludeInlineTestsWithName
+    IncludeInlineTestsWithName,
+    SuppressSourceInfoAnnotation
   ).foreach(_.addOptions(parser))
 
   parser.note("CIRCT (MLIR FIRRTL Compiler) options")