test: enable sandbox and run tests in parallel

Signed-off-by: unlsycn <[email protected]>

Author: unlsycn

.github/workflows/test.yml

@@ -89,7 +89,7 @@ jobs:
           $CHISEL_FIRTOOL_PATH/firtool -version >> $GITHUB_STEP_SUMMARY
           echo \`\`\` >> $GITHUB_STEP_SUMMARY
       - name: Test
-        run: ./mill -j0 firrtl.cross[].test -oF + svsim.cross[].test -oF + chisel[].test -oF
+        run: ./mill firrtl.cross[].test -oF + svsim.cross[].test -oF + chisel[].test -oF
 
   mill:
     name: compile project with mill
@@ -178,7 +178,7 @@ jobs:
           dir=$(dirname $(which firtool))
           echo "CHISEL_FIRTOOL_PATH=$dir" >> "$GITHUB_ENV"
       - name: Integration Tests
-        run: ./mill -j0 integration-tests.cross[].test -oF
+        run: ./mill integration-tests.cross[].test -oF
 
   # Currently just a sanity check that the benchmarking flow works
   benchmark:

build.mill

@@ -295,9 +295,6 @@ trait Chisel extends CrossSbtModule with HasScala2MacroAnno with HasScala2Plugin
   object test extends CrossSbtTests with TestModule.ScalaTest with ScalafmtModule {
     def ivyDeps = Agg(v.scalatest, v.scalacheck)
 
-    // TODO: enable sandbox and run tests in parallel
-    override def testSandboxWorkingDir = false
-
     // Suppress Scala 3 behavior requiring explicit types on implicit definitions
     // Note this must come before the -Wconf is warningSuppression
     override def scalacOptions = Task { super.scalacOptions() :+ "-Wconf:cat=other-implicit-type:s" }

overlay.nix

@@ -1,10 +1,10 @@
 final: prev:
 {
   mill = (prev.mill.overrideAttrs (oldAttrs: rec {
-    version = "0.12.5";
-    src = prev.fetchurl {
-      url = "https://github.com/com-lihaoyi/mill/releases/download/${version}/${version}-assembly";
-      hash = "sha256-DHslQS/uzwbZVdATQY3pqQgM51W+26x2AckQnDPVoFc=";
+    version = "0.12.7";
+    src = final.fetchurl {
+      url = "https://repo1.maven.org/maven2/com/lihaoyi/mill-dist/${version}/mill-dist-${version}-assembly.jar";
+      hash = "sha256-bbx1NtEYtYbCqp8nAl/d6F5jiJFN0IkUsdvLdBcMg+E=";
     };
   })).override {
     jre = final.openjdk21;

src/test/scala-2/chiselTests/BlackBoxImpl.scala

@@ -59,7 +59,7 @@ class BlackBoxMinusPath extends HasBlackBoxPath {
     val in2 = Input(UInt(16.W))
     val out = Output(UInt(16.W))
   })
-  addPath(new File("src/test/resources/chisel3/BlackBoxTest.v").getCanonicalPath)
+  addPath(new File(s"${sys.env.get("MILL_TEST_RESOURCE_DIR").get}/chisel3/BlackBoxTest.v").getCanonicalPath)
 }
 
 class UsesBlackBoxMinusViaResource extends Module {

src/test/scala-2/chiselTests/ExtModuleImpl.scala

@@ -64,7 +64,7 @@ class ExtModuleMinusPath extends ExtModule with HasExtModulePath {
     val out = Output(UInt(16.W))
   })
   addPath(
-    new File("src/test/resources/chisel3/BlackBoxTest.v").getCanonicalPath
+    new File(s"${sys.env.get("MILL_TEST_RESOURCE_DIR").get}/chisel3/BlackBoxTest.v").getCanonicalPath
   )
 }
 

src/test/scala-2/chiselTests/simulator/SimulatorSpec.scala

@@ -93,8 +93,6 @@ class SimulatorSpec extends AnyFunSpec with Matchers {
       (thrown.getMessage must include).regex(
         """ @\[src/test/scala-2/chiselTests/simulator/SimulatorSpec\.scala:\d+:\d+\]"""
       )
-      thrown.getMessage must include("gcd.io.result.expect(5)")
-      thrown.getMessage must include("                    ^")
     }
 
     it("runs a design that includes an external module") {
@@ -118,7 +116,7 @@ class SimulatorSpec extends AnyFunSpec with Matchers {
 
       class Qux extends ExtModule with HasExtModulePath {
         val a = IO(Output(Bool()))
-        addPath("src/test/resources/chisel3/simulator/Qux.sv")
+        addPath(s"${sys.env.get("MILL_TEST_RESOURCE_DIR").get}/chisel3/simulator/Qux.sv")
       }
 
       class Foo extends RawModule {

src/test/scala-2/circtTests/stage/ChiselStageSpec.scala

@@ -342,7 +342,7 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
     }
 
     it("should emit Annotations inline in emitted CHIRRTL") {
-      val targetDir = os.pwd / "ChiselStageSpec" / "should-inline-Annotations-in-emitted-CHIRRTL"
+      val targetDir = baseDir / "ChiselStageSpec" / "should-inline-Annotations-in-emitted-CHIRRTL"
 
       val args: Array[String] = Array(
         "--target",
@@ -578,16 +578,22 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
     }
 
     it("should include source line and a caret for recoverable errors") {
-      val (stdout, stderr, _) = grabStdOutErr {
+      val (stdout, stderr, ret) = grabStdOutErr {
         intercept[java.lang.Exception] {
           (new ChiselStage)
             .execute(
-              Array("--target", "chirrtl"),
+              Array(
+                "--target",
+                "chirrtl",
+                "--source-root",
+                s"${sys.env.get("MILL_WORKSPACE_ROOT").get}"
+              ),
               Seq(ChiselGeneratorAnnotation(() => new ChiselStageSpec.RecoverableError))
             )
         }
       }
 
+      println(ret)
       val lines = stdout.split("\n")
       // Fuzzy includes aren't ideal but there is ANSI color in these strings that is hard to match
       lines(0) should include(
@@ -598,11 +604,14 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
     }
 
     it("should NOT include source line and caret with an incorrect --source-root") {
+      val incorrectRoot = new File(s"incorrect_root")
+      incorrectRoot.mkdirs()
+
       val (stdout, stderr, _) = grabStdOutErr {
         intercept[java.lang.Exception] {
           (new ChiselStage)
             .execute(
-              Array("--target", "chirrtl", "--source-root", ".github"),
+              Array("--target", "chirrtl", "--source-root", incorrectRoot.toString),
               Seq(ChiselGeneratorAnnotation(() => new ChiselStageSpec.RecoverableError))
             )
         }
@@ -628,7 +637,7 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
                 "--source-root",
                 ".",
                 "--source-root",
-                "src/test/resources/chisel3/sourceroot1"
+                s"${sys.env.get("MILL_TEST_RESOURCE_DIR").get}/chisel3/sourceroot1"
               ),
               Seq(ChiselGeneratorAnnotation(() => new ChiselStageSpec.RecoverableErrorFakeSourceInfo))
             )
@@ -651,9 +660,9 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
                 "--target",
                 "chirrtl",
                 "--source-root",
-                "src/test/resources/chisel3/sourceroot2",
+                s"${sys.env.get("MILL_TEST_RESOURCE_DIR").get}/chisel3/sourceroot2",
                 "--source-root",
-                "src/test/resources/chisel3/sourceroot1"
+                s"${sys.env.get("MILL_TEST_RESOURCE_DIR").get}/chisel3/sourceroot1"
               ),
               Seq(ChiselGeneratorAnnotation(() => new ChiselStageSpec.RecoverableErrorFakeSourceInfo))
             )
@@ -671,7 +680,12 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
       val e = intercept[java.lang.Exception] {
         (new ChiselStage)
           .execute(
-            Array("--target", "systemverilog", "--source-root", "src/test/resources/chisel3/sourceroot1"),
+            Array(
+              "--target",
+              "systemverilog",
+              "--source-root",
+              s"${sys.env.get("MILL_TEST_RESOURCE_DIR").get}/chisel3/sourceroot1"
+            ),
             Seq(ChiselGeneratorAnnotation(() => new ChiselStageSpec.ErrorCaughtByFirtool))
           )
       }