Rename and fix firrtl emission for HierarchicalModuleName (#4872)

Author: jackkoenig

core/src/main/scala/chisel3/Printable.scala

@@ -193,9 +193,10 @@ object Printable {
   /** Resolve Printables that are resolved at Chisel-time */
   private[chisel3] def resolve(pable: Printable, ctx: Component)(implicit info: SourceInfo): Printable =
     pable.map {
-      case Name(data)     => PString(data.ref.name)
-      case FullName(data) => PString(data.ref.fullName(ctx))
-      case other          => other
+      case Name(data)             => PString(data.ref.name)
+      case FullName(data)         => PString(data.ref.fullName(ctx))
+      case HierarchicalModuleName => PString("{{HierarchicalModuleName}}")
+      case other                  => other
     }
 }
 
@@ -377,7 +378,7 @@ case object Percent extends Printable {
 }
 
 /** Represents the hierarchical name in the Verilog (`%m`) */
-case object HierarchicalName extends Printable {
+case object HierarchicalModuleName extends Printable {
   @deprecated("Use unpack with no arguments instead.", "Chisel 7.0.0")
   final def unpack(ctx: Component)(implicit info: SourceInfo): (String, Iterable[String]) = ("%m", List.empty)
   @deprecated("Use unpack with no arguments instead.", "Chisel 7.0.0")

core/src/main/scala/chisel3/package.scala

@@ -247,7 +247,7 @@ package object chisel3 {
               } else if (s(end + 1) == '%') {
                 Percent
               } else if (s(end + 1) == 'm') {
-                HierarchicalName
+                HierarchicalModuleName
               } else {
                 throw new UnknownFormatConversionException("Un-escaped %")
               }

docs/src/explanations/printing.md

@@ -61,11 +61,11 @@ printf(cf"myUInt = $myUInt%c") // myUInt = !
 
 There are special values you can include in your `cf` interpolated string:
 
-* `HierarchicalName` (`%m`): The hierarchical name of the signal
+* `HierarchicalModuleName` (`%m`): The hierarchical name of the current module
 * `Percent` (`%%`): A literal `%`
 
 ```scala mdoc:compile-only
-printf(cf"hierarchical path = $HierarchicalName\n") // hierarchical path = <verilog.module.path>
+printf(cf"hierarchical path = $HierarchicalModuleName\n") // hierarchical path = <verilog.module.path>
 printf(cf"hierarchical path = %m\n") // equivalent to the above
 
 printf(cf"100$Percent\n") // 100%

src/test/scala-2/chiselTests/PrintableSpec.scala

@@ -318,13 +318,20 @@ class PrintableSpec extends AnyFlatSpec with Matchers with FileCheck {
   it should "support all legal format specifiers" in {
     class MyModule extends Module {
       val in = IO(Input(UInt(8.W)))
-      printf(cf"$HierarchicalName $in%d $in%x $in%b $in%c %%\n")
+      printf(cf"$HierarchicalModuleName $in%d $in%x $in%b $in%c %%\n")
     }
     ChiselStage
       .emitCHIRRTL(new MyModule)
       .fileCheck()(
-        """CHECK: printf(clock, UInt<1>(0h1), "%m %d %x %b %c %%\n", in, in, in, in)"""
+        """CHECK{LITERAL}: printf(clock, UInt<1>(0h1), "{{HierarchicalModuleName}} %d %x %b %c %%\n", in, in, in, in)"""
       )
+    // Also check Verilog
+    ChiselStage
+      .emitSystemVerilog(new MyModule)
+      .fileCheck()(
+        """CHECK: $fwrite(`PRINTF_FD_, "%m %d %x %b %c %%\n", in, in, in, in);"""
+      )
+
   }
 
   it should "support modifiers to format specifiers" in {
@@ -383,7 +390,7 @@ class PrintableSpec extends AnyFlatSpec with Matchers with FileCheck {
       (Character(x), ("%c", Seq(x))),
       (PString("foo"), ("foo", Seq())),
       (Percent, ("%%", Seq())),
-      (HierarchicalName, ("%m", Seq())),
+      (HierarchicalModuleName, ("%m", Seq())),
       (Name(x), ("%n", Seq(x))),
       (FullName(x), ("%N", Seq(x)))
     )

src/test/scala-2/chiselTests/Printf.scala

@@ -81,7 +81,13 @@ class PrintfSpec extends AnyFlatSpec with Matchers with FileCheck {
     ChiselStage
       .emitCHIRRTL(new MyModule)
       .fileCheck()(
-        """CHECK: printf(clock, UInt<1>(0h1), "%m %d %x %b %c %%\n", in, in, in, in)"""
+        """CHECK{LITERAL}: printf(clock, UInt<1>(0h1), "{{HierarchicalModuleName}} %d %x %b %c %%\n", in, in, in, in)"""
+      )
+    // Also check Verilog
+    ChiselStage
+      .emitSystemVerilog(new MyModule)
+      .fileCheck()(
+        """CHECK: $fwrite(`PRINTF_FD_, "%m %d %x %b %c %%\n", in, in, in, in);"""
       )
   }