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Add AutoBlackbox (#4495)
* feat: add SlangUtils to extract metadata from Verilog * feat: add AutoBlackBox * feat: allow overriding source locator in module Signed-off-by: unlsycn <[email protected]> * feat: add AutoBlackBoxSpec Signed-off-by: unlsycn <[email protected]> * ci: build and cache slang in workflow Signed-off-by: unlsycn <[email protected]> --------- Signed-off-by: unlsycn <[email protected]> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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‎.github/workflows/build-slang/action.yml‎

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name: Build Slang
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inputs:
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version:
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description: 'version to install'
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required: false
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default: '7.0'
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runs:
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using: composite
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steps:
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- id: cache-slang
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uses: actions/cache@v4
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with:
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path: /usr/local/bin/slang
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key: slang-${{ runner.os }}-${{ inputs.version }}
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- name: Build from source
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shell: bash
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if: steps.cache-slang.outputs.cache-hit != 'true'
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run: |
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cd /tmp
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wget -q https://github.com/MikePopoloski/slang/archive/refs/tags/v${{ inputs.version }}.tar.gz -O slang.tar.gz
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tar xf slang.tar.gz
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cd slang-${{ inputs.version }}
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cmake -B build
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cmake --build build
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cd build && ctest --output-on-failure
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cp bin/slang /usr/local/bin/slang
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slang || true

‎.github/workflows/ci-circt-nightly.yml‎

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@@ -51,6 +51,7 @@ jobs:
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jvm: [8]
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scala: ["2.13.15"]
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espresso: ["2.4"]
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slang: ["7.0"]
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circt: ["nightly"]
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ref: ${{ fromJSON(needs.determine-branch.outputs.branches) }}
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uses: ./.github/workflows/test.yml
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jvm: ${{ matrix.jvm }}
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scala: ${{ matrix.scala }}
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espresso: ${{ matrix.espresso }}
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slang: ${{ matrix.slang }}
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circt: ${{ matrix.circt }}
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ref: ${{ matrix.ref }}
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‎.github/workflows/ci.yml‎

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jvm: [8]
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scala: ["2.13.15"]
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espresso: ["2.4"]
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slang: ["7.0"]
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uses: ./.github/workflows/test.yml
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with:
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system: ${{ matrix.system }}
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jvm: ${{ matrix.jvm }}
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scala: ${{ matrix.scala }}
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espresso: ${{ matrix.espresso }}
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slang: ${{ matrix.slang }}
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# Sentinel job to simplify how we specify which checks need to pass in branch
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# protection and in Mergify. This job checks that all matrix jobs were

‎.github/workflows/test.yml‎

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default: '2.4'
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required: true
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type: string
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slang:
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description: 'The slang version to use'
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default: '7.0'
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required: true
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type: string
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circt:
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description: 'The CIRCT version to use (must be a valid release tag, "nightly", or "version-file").
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Leave off (or empty) to let Chisel manage the CIRCT version'
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uses: ./.github/workflows/install-espresso
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with:
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version: ${{ inputs.espresso }}
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- name: Install Slang
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uses: ./.github/workflows/build-slang
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with:
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version: ${{ inputs.slang }}
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- name: Setup Java
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uses: actions/setup-java@v4
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with:

‎plugin/src/main/scala/chisel3/internal/plugin/ChiselComponent.scala‎

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@@ -244,7 +244,10 @@ class ChiselComponent(val global: Global, arguments: ChiselPluginArguments)
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super.transform(tree)
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}
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// Also look for Module class definitions for inserting source locators
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case module: ClassDef if isAModule(module.symbol) && !module.mods.hasFlag(Flag.ABSTRACT) =>
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case module: ClassDef
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if isAModule(module.symbol) && !module.mods.hasFlag(
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Flag.ABSTRACT
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) && !isOverriddenSourceLocator(module.impl) =>
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val path = SourceInfoFileResolver.resolve(module.pos.source)
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val info = localTyper.typed(q"chisel3.experimental.SourceLine($path, ${module.pos.line}, ${module.pos.column})")
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‎plugin/src/main/scala/chisel3/internal/plugin/ChiselUtils.scala‎

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@@ -61,5 +61,8 @@ private[plugin] trait ChiselOuterUtils { outerSelf: TypingTransformers =>
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def isNullaryMethodNamed(name: String, defdef: DefDef): Boolean =
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defdef.name.decodedName.toString == name && defdef.tparams.isEmpty && defdef.vparamss.isEmpty
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def isOverriddenSourceLocator(impl: Template) = impl.body
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.exists(m => m.symbol != null && m.symbol.name.toString == "_sourceInfo")
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}
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}

‎src/main/scala/chisel3/util/experimental/AutoBlackBox.scala‎

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// SPDX-License-Identifier: Apache-2.0
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package chisel3.util.experimental
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import chisel3._
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import scala.collection.immutable.SeqMap
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import chisel3.experimental.SourceInfo
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class AutoBlackBox(
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val verilog: String,
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val signalFilter: String => Boolean = _ => true
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)(
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implicit val __sourceInfo: SourceInfo)
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extends FixedIOExtModule(
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ioGenerator = new AutoBundleFromVerilog(
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SeqMap.from(SlangUtils.verilogModuleIO(SlangUtils.getVerilogAst(verilog)))
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)(signalFilter)
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) {
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override def desiredName = SlangUtils.verilogModuleName(SlangUtils.getVerilogAst(verilog))
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override def _sourceInfo = __sourceInfo
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}
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class AutoBundleFromVerilog(
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allElements: SeqMap[String, Data]
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)(signalFilter: String => Boolean)
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extends Record {
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val elements: SeqMap[String, Data] = allElements.filter(n => signalFilter(n._1)).map {
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case (k, v) =>
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k -> chisel3.reflect.DataMirror.internal.chiselTypeClone(v)
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}
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def apply(data: String) = elements.getOrElse(
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data,
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throw new ChiselException(
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s"$data not found in Verilog IO: \n ${allElements.keys.mkString("\n")}"
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)
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)
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}

‎src/main/scala/chisel3/util/experimental/SlangUtils.scala‎

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// SPDX-License-Identifier: Apache-2.0
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package chisel3.util.experimental
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import chisel3._
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import chisel3.experimental.{Analog, DoubleParam, IntParam, Param, StringParam}
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import ujson.Value.Value
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import scala.collection.immutable.SeqMap
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object SlangUtils {
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/** Use Slang to parse Verilog into Json AST. */
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def getVerilogAst(verilog: String): Value = {
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val astFile = os.temp()
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os.proc(
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"slang",
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os.temp(verilog),
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"--single-unit",
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"--ignore-unknown-modules",
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"--compat",
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"vcs",
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"--ast-json",
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astFile
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).call()
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ujson.read(os.read(astFile))
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}
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/** Extract IO from Verilog AST. */
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def verilogModuleIO(verilogAst: Value): SeqMap[String, Data] = {
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verilogAst.obj("design").obj("members").arr.flatMap {
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case value: ujson.Obj if value.value("kind").strOpt.contains("Instance") =>
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value.value("body").obj.value("members").arr.flatMap {
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case value: ujson.Obj if value.value("kind").strOpt.contains("Port") =>
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Some(
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value.value("name").str -> {
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val width: Int =
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"""logic\[(?<MSB>\d+):(?<LSB>\d+)\]""".r
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.findFirstMatchIn(value.value("type").str) match {
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case Some(m) =>
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m.group("MSB").toInt - m.group("LSB").toInt + 1
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case None =>
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value.value("type").str match {
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case "logic" => 1
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case _ =>
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throw new ChiselException(
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s"Unhandled type ${value.value("type").str}"
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)
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}
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}
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value.value("direction").str match {
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case "In" => Input(UInt(width.W))
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case "Out" => Output(UInt(width.W))
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case "InOut" => Analog(width.W)
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}
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}
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)
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case _ => None
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}
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case _ => None
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}
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}.to(collection.immutable.SeqMap)
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/** Extract module name from Verilog AST. */
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def verilogModuleName(verilogAst: Value): String = {
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val names = verilogAst.obj("design").obj("members").arr.flatMap {
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case value: ujson.Obj if value.value("kind").strOpt.contains("Instance") =>
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Some(value.value("name").str)
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case _ => None
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}
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require(names.length == 1, "only support one verilog module currently")
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names.head
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}
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/** Extract module parameter from Verilog AST. */
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def verilogParameter(verilogAst: Value): Seq[(String, Param)] = {
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verilogAst.obj("design").obj("members").arr.flatMap {
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case value: ujson.Obj if value.value("kind").strOpt.contains("Instance") =>
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value.value("body").obj.value("members").arr.flatMap {
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case value: ujson.Obj if value.value("kind").strOpt.contains("Parameter") =>
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Some(value.value("name").str -> (value.value("type").str match {
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case "real" => DoubleParam(value.value("value").str.toDouble)
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case "string" =>
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StringParam(
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value.value("value").str.stripPrefix("\"").stripSuffix("\"")
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)
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case "int" => IntParam(BigInt(value.value("value").str.toInt))
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case lit =>
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throw new ChiselException(
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s"unsupported literal: $lit in\n ${ujson.reformat(value, 2)}"
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)
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}))
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case _ => None
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}
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case _ => None
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}
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}.toSeq
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}

‎src/test/scala/chiselTests/experimental/AutoBlackBoxSpec.scala‎

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// SPDX-License-Identifier: Apache-2.0
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package chiselTests.experimental
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import chisel3.util.experimental.AutoBlackBox
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import chiselTests.ChiselFlatSpec
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import circt.stage.ChiselStage
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import chisel3.experimental.hierarchy.Instantiate
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import chisel3.experimental.SourceLine
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class AutoBlackBoxSpec extends ChiselFlatSpec {
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"AutoBlackBox" should "generate IO, module name and parameter" in {
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assert(
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ChiselStage
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.emitCHIRRTL(
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new chisel3.Module {
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implicit val info = SourceLine("Foo.scala", 1, 2)
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Instantiate(
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new AutoBlackBox(
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"""module BlackBoxPassthrough
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|#(
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|parameter int width = 2,
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|parameter real pi = 3.14 + 1,
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|parameter string str = "abc"
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|)
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|(
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| input [width-1:0] in,
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| output [width-1:0] out,
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| inout VDD,
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| inout VSS
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|);
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| assign out = in;
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|endmodule
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|""".stripMargin,
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{
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case "VDD" => false
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case "VSS" => false
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case _ => true
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}
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)
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)
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}
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)
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.contains(
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"""extmodule BlackBoxPassthrough : @[Foo.scala 1:2]
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| output out : UInt<2>
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| input in : UInt<2>
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| defname = BlackBoxPassthrough
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|""".stripMargin
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)
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)
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}
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}

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