Fix boring taps of views of ExtModule ports (#5110)

Author: jackkoenig

core/src/main/scala/chisel3/RawModule.scala

@@ -193,13 +193,7 @@ abstract class RawModule extends BaseModule {
     _component
   }
 
-  private[chisel3] def secretConnection(left: Data, _right: Data)(implicit si: SourceInfo): Unit = {
-    val (right: Data, _) = chisel3.experimental.dataview
-      .reifyIdentityView(_right)
-      .getOrElse(
-        throwException(s"BoringUtils currently only support identity views, ${_right} has multiple targets.")
-      )
-
+  private[chisel3] def secretConnection(left: Data, right: Data)(implicit si: SourceInfo): Unit = {
     def computeConnection(left: Data, right: Data): Command = {
       (left.probeInfo.nonEmpty, right.probeInfo.nonEmpty) match {
         case (true, true)                                 => ProbeDefine(si, left.lref, Node(right))

src/main/scala/chisel3/util/experimental/BoringUtils.scala

@@ -7,7 +7,8 @@ import chisel3.probe.{Probe, RWProbe}
 import chisel3.reflect.DataMirror
 import chisel3.Data.ProbeInfo
 import chisel3.experimental.{annotate, requireIsHardware, skipPrefix, BaseModule, SourceInfo}
-import chisel3.internal.{Builder, BuilderContextCache, NamedComponent, Namespace}
+import chisel3.experimental.dataview.reifyIdentityView
+import chisel3.internal.{throwException, Builder, BuilderContextCache, NamedComponent, Namespace}
 import chisel3.internal.binding.{BlockBinding, CrossModuleBinding, PortBinding, SecretPortBinding}
 import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation}
 import chisel3.internal.firrtl.ir.Block
@@ -209,12 +210,18 @@ object BoringUtils {
   }
 
   private def boreOrTap[A <: Data](
-    source:      A,
+    _source:     A,
     createProbe: Option[ProbeInfo] = None,
     isDrive:     Boolean = false
   )(
     implicit si: SourceInfo
   ): A = {
+    val (source, _) =
+      reifyIdentityView(_source)
+        .getOrElse(
+          throwException(s"BoringUtils currently only support identity views, ${_source} has multiple targets.")
+        )
+
     def parent(d: Data): BaseModule = d.topBinding.location.get
     def purePortTypeBase = if (createProbe.nonEmpty) Output(chiselTypeOf(source))
     else if (DataMirror.hasOuterFlip(source)) Flipped(chiselTypeOf(source))

src/test/scala-2/chiselTests/BoringUtilsTapSpec.scala

@@ -358,6 +358,34 @@ class BoringUtilsTapSpec extends AnyFlatSpec with Matchers with FileCheck {
       )
   }
 
+  it should "work for identity views of ExtModule ports" in {
+    import chisel3.experimental.dataview._
+    class Foo extends ExtModule {
+      val out = IO(Output(Bool()))
+      val view = out.viewAs[Bool]
+    }
+    class Top extends RawModule {
+      val foo = Module(new Foo)
+      val outProbe = IO(probe.Probe(Bool()))
+      val out = IO(Bool())
+      probe.define(outProbe, BoringUtils.tap(foo.view))
+      out := BoringUtils.tapAndRead(foo.view)
+    }
+    ChiselStage
+      .emitCHIRRTL(new Top, args = Array("--full-stacktrace"))
+      .fileCheck()(
+        """|CHECK: extmodule Foo :
+           |CHECK:   output out : UInt<1>
+           |CHECK: public module Top :
+           |CHECK:   output outProbe : Probe<UInt<1>>
+           |CHECK:   output out : UInt<1>
+           |CHECK:   inst foo of Foo
+           |CHECK:   define outProbe = probe(foo.out)
+           |CHECK:   connect out, foo.out
+           |""".stripMargin
+      )
+  }
+
   it should "NOT work [yet] for non-identity views" in {
     import chisel3.experimental.dataview._
     class MyBundle extends Bundle {