Tip when running out of memory creating ROMs in peek-poke less tests

[oharboe]

Without the InlineInstance below, I run out of memory as Chisel + firtool then can't figure out to make a ROM (SystemVerilog array) and Verilator then creates one multiplier per expected entry :-)

The Mul below is a lowered multiplication, by our Chisel code, so the below evaluates to a fantastic amount of .fir code that, I believe, firtool is evaluating to a ROM.

This sort of test-code is very memory intensive, which is surprising, but understandable.

  val expected = VecInit(inputs.map { inputs =>
    val mul = Module(new Mul(arch.Data) with InlineInstance)
    mul.io.srcs := inputs
    mul.io.operation := MulOperation.Lo
    mul.io.dst
  })