[src] Source sda_oe from a register and hard-wire I3C Target

- Remove the sda_oe comb logic to bus_tx_flow and put it behind a
  register
- Hard-wire the I3C Target device to the pads for de-risking

Signed-off-by: Florian Glaser <glaserf@lowrisc.org>

Author: glaserf

src/ctrl/bus_tx_flow.sv

@@ -34,6 +34,9 @@ module bus_tx_flow import i3c_pkg::*; (
   // Open Drain / Push Pull
   output logic sel_od_pp_o,
 
+  // Output enable for SDA pad
+  output logic sda_oe_o,
+
   // Output I3C SDA bus line
   output logic sda_o
 );
@@ -42,14 +45,16 @@ module bus_tx_flow import i3c_pkg::*; (
   logic       bit_counter_en;
   logic [3:0] bit_counter_q, bit_counter_d;
 
+  // Registers for all critical signals directly connected to the SDA pad
   i3c_byte_t  req_value_q, req_value_d;
   i3c_drive_e drive_mode_q, drive_mode_d;
+  logic       sda_oe_q, sda_oe_d;
 
   logic tx_done;     // Indicates finished bit write
   logic bus_tx_done; // Feedback to requester that transfer is done
   logic req_error;
 
-  // TODO
+  // TODO Can probably be removed
   assign req_error = 1'b0;
 
   typedef enum logic [2:0] {
@@ -63,6 +68,24 @@ module bus_tx_flow import i3c_pkg::*; (
 
   tx_state_e state_d, state_q;
 
+  // SDA is simply the MSB of the data shift register. No further logic or muxing.
+  // Similar for pad drive mode and output enable.
+  assign sda_o = req_value_q[7];
+  assign sel_od_pp_o = drive_mode_q;
+  assign sda_oe_o = sda_oe_q;
+
+  /*
+    Truth table for sda_oe.
+
+    sel_od_pp_o | sda_o  || sda_oe_o | IO state
+    ------------+--------++----------+-----------
+         0      |   0    ||    1     |    0
+         0      |   1    ||    0     |   hi-z
+         1      |   0    ||    1     |    0
+         1      |   1    ||    1     |    1
+  */
+  assign sda_oe_d = drive_mode_d || !req_value_d[7];
+
   // Common logic whenever a transfer gets started, including back-to-back transfers
   function automatic tx_state_e start_transfer(
     input  bus_tx_req_t bus_tx_req,
@@ -122,7 +145,6 @@ module bus_tx_flow import i3c_pkg::*; (
 
   endfunction : start_transfer
 
-
   // Bit counter used for byte transfers
   always_comb begin
     bit_counter_d = bit_counter_q;
@@ -136,10 +158,7 @@ module bus_tx_flow import i3c_pkg::*; (
     end
   end
 
-  // SDA is simply the MSB of the data shift register. No further logic or muxing.
-  assign sda_o = req_value_q[7];
-  assign sel_od_pp_o = drive_mode_q;
-
+  // Main FSM which handles all low-level bus details in terms of transmitting
   always_comb begin : tx_fsm
     bit_counter_en = 1'b0;
 
@@ -289,11 +308,13 @@ module bus_tx_flow import i3c_pkg::*; (
       bit_counter_q <= '0;
       req_value_q   <= '1;
       drive_mode_q  <= OpenDrain;
+      sda_oe_q      <= 1'b0;
       state_q       <= Idle;
     end else begin
       bit_counter_q <= bit_counter_d;
       req_value_q   <= req_value_d;
       drive_mode_q  <= drive_mode_d;
+      sda_oe_q      <= sda_oe_d;
       state_q       <= state_d;
     end
   end

src/ctrl/controller.sv

@@ -67,6 +67,7 @@ module controller
     input  logic sda_i,
     output logic scl_o,
     output logic sda_o,
+    output logic sda_oe_o,
     output logic sel_od_pp_o,
     input logic arbitration_lost_i,
 
@@ -271,6 +272,8 @@ module controller
     output logic in_hdr_mode_o
 );
 
+  localparam int unsigned RecoveryMode = 'h3;
+
   logic phy_en;
   logic [1:0] phy_mux_select;
   logic i2c_active_en;
@@ -339,25 +342,30 @@ module controller
   bus_state_t ctrl_bus_i[4];
   logic ctrl_scl_o[4];
   logic ctrl_sda_o[4];
+  logic ctrl_sda_oe_o[4];
   logic ctrl_sel_od_pp_i[4];
 
-  localparam int unsigned RecoveryMode = 'h3;
-  always_comb begin : mux_4_to_1
-    scl_o = ctrl_scl_o[phy_mux_select];
-    sda_o = ctrl_sda_o[phy_mux_select];
-    sel_od_pp_o = ctrl_sel_od_pp_i[phy_mux_select];
+  assign ctrl_sda_oe_o[0] = 1'b0;
+  assign ctrl_sda_oe_o[1] = 1'b0;
 
+  // NOTE: For now, the I3C standby (target) device is hard-wired onto the bus for risk mitigation
+  assign scl_o = ctrl_scl_o[3];
+  assign sda_o = ctrl_sda_o[3];
+  assign sda_oe_o    = ctrl_sda_oe_o[3];
+  assign sel_od_pp_o = ctrl_sel_od_pp_i[3];
+
+  assign ctrl_bus_i[3] = bus;
+
+  // Tieoff of all other devices
+  always_comb begin : mux_tieoff
     // Default
-    for (int i=0; i<4; i++) begin
-        ctrl_bus_i[i] = '0;
-        ctrl_bus_i[i].sda.value = '1;
-        ctrl_bus_i[i].scl.value = '1;
-        ctrl_bus_i[i].sda.stable_high = '1;
-        ctrl_bus_i[i].scl.stable_high = '1;
+    for (int i=0; i<3; i++) begin
+      ctrl_bus_i[i] = '0;
+      ctrl_bus_i[i].sda.value = 1'b1;
+      ctrl_bus_i[i].scl.value = 1'b1;
+      ctrl_bus_i[i].sda.stable_high = 1'b1;
+      ctrl_bus_i[i].scl.stable_high = 1'b1;
     end
-
-    // Muxed
-    ctrl_bus_i[phy_mux_select] = bus;
   end
 
   configuration xconfiguration (
@@ -496,6 +504,7 @@ module controller
       .ctrl_bus_i(ctrl_bus_i[2:3]),
       .ctrl_scl_o(ctrl_scl_o[2:3]),
       .ctrl_sda_o(ctrl_sda_o[2:3]),
+      .ctrl_sda_oe_o(ctrl_sda_oe_o[2:3]),
       .phy_sel_od_pp_o(ctrl_sel_od_pp_i[2:3]),
       .arbitration_lost_i(arbitration_lost_i),
       .rx_desc_queue_full_i(tti_rx_desc_queue_full_i),

src/ctrl/controller_standby.sv

@@ -34,6 +34,7 @@ module controller_standby
     input bus_state_t ctrl_bus_i[2],
     output logic ctrl_scl_o[2],
     output logic ctrl_sda_o[2],
+    output logic ctrl_sda_oe_o[2],
     output logic phy_sel_od_pp_o[2],
     input logic arbitration_lost_i,
 
@@ -327,6 +328,8 @@ module controller_standby
     .source_data_o(tx_queue_rdata_int)
   );
 
+  assign ctrl_sda_oe_o[0] = 1'b0;
+
   controller_standby_i2c #(
       .TtiRxDescDataWidth(TtiRxDescDataWidth),
       .TtiTxDescDataWidth(TtiTxDescDataWidth),
@@ -421,6 +424,7 @@ module controller_standby
       .ctrl_bus_i(ctrl_bus_i[1]),
       .ctrl_scl_o(ctrl_scl_o[1]),
       .ctrl_sda_o(ctrl_sda_o[1]),
+      .ctrl_sda_oe_o(ctrl_sda_oe_o[1]),
       .arbitration_lost_i(arbitration_lost_i),
       .phy_sel_od_pp_o(phy_sel_od_pp_o[1]),
       .rx_desc_queue_wvalid_o(i3c_rx_desc_queue_wvalid_o),

src/ctrl/controller_standby_i3c.sv

@@ -23,6 +23,7 @@ module controller_standby_i3c
     input  bus_state_t ctrl_bus_i,
     output logic       ctrl_scl_o,
     output logic       ctrl_sda_o,
+    output logic       ctrl_sda_oe_o,
     output logic       phy_sel_od_pp_o,
     input  logic       arbitration_lost_i,
 
@@ -609,6 +610,7 @@ module controller_standby_i3c
     .tx_rsp_o(bus_tx_rsp),
 
     .sel_od_pp_o(phy_sel_od_pp_o),
+    .sda_oe_o   (ctrl_sda_oe_o),
     .sda_o      (ctrl_sda_o)
   );
 

src/i3c.sv

@@ -190,6 +190,7 @@ module i3c
     input  logic i3c_sda_i,  // serial data input from i3c bus
     output logic i3c_sda_o,  // serial data output to i3c bus
 
+    output logic i3c_sda_oe_o, // Pad output enable
     output logic sel_od_pp_o,  // 0 - Open Drain, 1 - Push Pull
 
     // DAT memory export interface
@@ -478,6 +479,7 @@ module i3c
   logic ctrl2phy_scl;
   logic ctrl2phy_sda;
   logic ctrl_sel_od_pp;
+  logic ctrl_sda_oe;
 
   // Configuration
   logic phy_en;
@@ -590,6 +592,7 @@ module i3c
       .sda_i(phy2ctrl_sda),
       .scl_o(ctrl2phy_scl),
       .sda_o(ctrl2phy_sda),
+      .sda_oe_o(ctrl_sda_oe),
       .sel_od_pp_o(ctrl_sel_od_pp),
       .arbitration_lost_i(arbitration_lost_q),
 
@@ -1288,6 +1291,8 @@ module i3c
       .ctrl_sda_i(ctrl2phy_sda),
       .ctrl_scl_o(phy2ctrl_scl),
       .ctrl_sda_o(phy2ctrl_sda),
+      .ctrl_sda_oe_i(ctrl_sda_oe),
+      .ctrl_sda_oe_o(i3c_sda_oe_o),
       .sel_od_pp_i(ctrl_sel_od_pp),
       .sel_od_pp_o(sel_od_pp_o)
   );

src/i3c_wrapper.sv

@@ -217,11 +217,12 @@ module i3c_wrapper #(
 `endif
 `endif
 
-      .i3c_scl_i  (scl_i),
-      .i3c_scl_o  (scl_o),
-      .i3c_sda_i  (sda_i),
-      .i3c_sda_o  (sda_o),
-      .sel_od_pp_o(sel_od_pp_o),
+      .i3c_scl_i   (scl_i),
+      .i3c_scl_o   (scl_o),
+      .i3c_sda_i   (sda_i),
+      .i3c_sda_o   (sda_o),
+      .i3c_sda_oe_o(sda_oe),
+      .sel_od_pp_o (sel_od_pp_o),
 
       .dat_mem_src_i (dat_mem_src),
       .dat_mem_sink_o(dat_mem_sink),
@@ -274,18 +275,7 @@ module i3c_wrapper #(
       .cfg_i('0)  // Unused
   );
 
-/*
-  Truth table.
 
-  sel_od_pp_o | sda_o  || sda_oe | IO state
-  ------------+--------++--------+-----------
-       0      |   0    ||   1    |    0
-       0      |   1    ||   0    |   hi-z
-       1      |   0    ||   1    |    0
-       1      |   1    ||   1    |    1
-*/
-
-  assign sda_oe = sel_od_pp_o || !sda_o;
   assign scl_oe = 1'b0;
 
 endmodule

src/phy/i3c_phy.sv

@@ -20,6 +20,10 @@ module i3c_phy (
     output logic ctrl_scl_o,
     output logic ctrl_sda_o,
 
+    // Pad output enable
+    input  logic ctrl_sda_oe_i,
+    output logic ctrl_sda_oe_o,
+
     // Open-Drain / Push-Pull control
     input  logic sel_od_pp_i,
     output logic sel_od_pp_o
@@ -59,5 +63,6 @@ module i3c_phy (
   assign sda_o = ctrl_sda_i;
   assign scl_o = ctrl_scl_i;
   assign sel_od_pp_o = sel_od_pp_i;
+  assign ctrl_sda_oe_o = ctrl_sda_oe_i;
 
 endmodule