first try to purge out ClockGroup

Author: sequencer

src/main/scala/subsystem/Attachable.scala

@@ -21,15 +21,18 @@ trait LazyScopeWithParameters extends LazyScope { this: LazyModule =>
   implicit val p: Parameters
 }
 
+/** provide [[anyLocationMap]] to store Locations. */
+trait HasLocations { this: LazyModule =>
+  val anyLocationMap = LocationMap.empty[Any]
+}
+
 /** Layers of hierarchy with this trait contain attachment points for neworks of power, clock, reset, and interrupt resources */
 trait HasPRCILocations extends LazyScopeWithParameters { this: LazyModule =>
-  val allClockGroupsNode: ClockGroupNode
   val ibus: InterruptBusWrapper
-  val anyLocationMap = LocationMap.empty[Any]
 }
 
 /** Layers of hierarchy with this trait contain attachment points for TileLink interfaces */
-trait HasTileLinkLocations extends HasPRCILocations { this: LazyModule =>
+trait HasTileLinkLocations extends HasLocations with LazyScope { this: LazyModule =>
   val busContextName: String
   val tlBusWrapperLocationMap = LocationMap.empty[TLBusWrapper]
   def locateTLBusWrapper(location: Location[TLBusWrapper]): TLBusWrapper = locateTLBusWrapper(location.name)
@@ -38,19 +41,19 @@ trait HasTileLinkLocations extends HasPRCILocations { this: LazyModule =>
 
 /** Subclasses of this trait have the ability to instantiate things inside a context that has TL attachement locations */
 trait CanInstantiateWithinContextThatHasTileLinkLocations {
-  def instantiate(context: HasTileLinkLocations)(implicit p: Parameters): Unit
+  def instantiate(context: HasTileLinkLocations with HasPRCILocations with LazyModule)(implicit p: Parameters): Unit
 }
 
 /** Subclasses of this trait have the ability to connect things inside a context that has TL attachement locations */
 trait CanConnectWithinContextThatHasTileLinkLocations {
-  def connect(context: HasTileLinkLocations)(implicit p: Parameters): Unit
+  def connect(context: HasTileLinkLocations with HasPRCILocations with LazyModule)(implicit p: Parameters): Unit
 }
 
 /** Attachable things provide a standard interface by which other things may attach themselves to this target.
   * Right now the trait is mostly for backwards compatibility, and in case it eventually becomes valuable
   * to be able to define additional resources available to agents trying to attach themselves, other than
   * what is being made available via the LocationMaps in trait HasTileLinkLocations.
   */
-trait Attachable extends HasTileLinkLocations { this: LazyModule =>
+trait Attachable extends HasTileLinkLocations with HasPRCILocations { this: LazyModule =>
   def locateTLBusWrapper(location: TLBusWrapperLocation): TLBusWrapper = locateTLBusWrapper(location.name)
 }

src/main/scala/subsystem/BankedCoherenceParams.scala

@@ -44,7 +44,7 @@ case class CoherenceManagerWrapperParams(
   extends HasTLBusParams 
   with TLBusWrapperInstantiationLike
 {
-  def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): CoherenceManagerWrapper = {
+  def instantiate(context: HasTileLinkLocations with HasPRCILocations with LazyModule, loc: Location[TLBusWrapper])(implicit p: Parameters): CoherenceManagerWrapper = {
     val cmWrapper = LazyModule(new CoherenceManagerWrapper(this, context))
     cmWrapper.suggestName(loc.name + "_wrapper")
     cmWrapper.halt.foreach { context.anyLocationMap += loc.halt(_) }
@@ -53,7 +53,7 @@ case class CoherenceManagerWrapperParams(
   }
 }
 
-class CoherenceManagerWrapper(params: CoherenceManagerWrapperParams, context: HasTileLinkLocations)(implicit p: Parameters) extends TLBusWrapper(params, params.name) {
+class CoherenceManagerWrapper(params: CoherenceManagerWrapperParams, context: HasTileLinkLocations with HasPRCILocations with LazyModule)(implicit p: Parameters) extends TLBusWrapper(params, params.name) {
   val (tempIn, tempOut, halt) = params.coherenceManager(context)
 
   private val coherent_jbar = LazyModule(new TLJbar)
@@ -68,7 +68,7 @@ class CoherenceManagerWrapper(params: CoherenceManagerWrapperParams, context: Ha
 }
 
 object CoherenceManagerWrapper {
-  type CoherenceManagerInstantiationFn = HasTileLinkLocations => (TLInwardNode, TLOutwardNode, Option[IntOutwardNode])
+  type CoherenceManagerInstantiationFn = HasTileLinkLocations with HasPRCILocations with LazyModule => (TLInwardNode, TLOutwardNode, Option[IntOutwardNode])
 
   def broadcastManagerFn(
     name: String,

src/main/scala/subsystem/BaseSubsystem.scala

@@ -10,7 +10,7 @@ import freechips.rocketchip.prci._
 import freechips.rocketchip.tilelink.TLBusWrapper
 import freechips.rocketchip.util._
 
-case object SubsystemDriveClockGroupsFromIO extends Field[Boolean](true)
+case object SubsystemDriveClockFromIO extends Field[Boolean](true)
 case class TLNetworkTopologyLocated(where: HierarchicalLocation) extends Field[Seq[CanInstantiateWithinContextThatHasTileLinkLocations with CanConnectWithinContextThatHasTileLinkLocations]]
 case class TLManagerViewpointLocated(where: HierarchicalLocation) extends Field[Location[TLBusWrapper]](SBUS)
 
@@ -54,26 +54,16 @@ case object SubsystemResetSchemeKey extends Field[SubsystemResetScheme](ResetSyn
   */
 trait HasConfigurablePRCILocations { this: HasPRCILocations =>
   val ibus = LazyModule(new InterruptBusWrapper)
-  val allClockGroupsNode = ClockGroupIdentityNode()
-  val io_clocks = if (p(SubsystemDriveClockGroupsFromIO)) {
-    val aggregator = ClockGroupAggregator()
-    val source = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
-    allClockGroupsNode :*= aggregator := source
-    Some(InModuleBody {
-      val elements = source.out.map(_._1.member.elements).flatten
-      val io = IO(Flipped(RecordMap(elements.map { case (name, data) =>
-        name -> data.cloneType
-      }:_*)))
-      elements.foreach { case (name, data) => io(name).foreach { data := _ } }
-      io
-    })
-  } else {
-    None
+  val prciClockNode = ClockAdapterNode()
+  val io_clocks = Option.when(p(SubsystemDriveClockFromIO)){
+    val source = ClockSourceNode(Seq(ClockSourceParameters()))
+    prciClockNode :*= source
+    InModuleBody(source.makeIOs())
   }
 }
 
 /** Look up the topology configuration for the TL buses located within this layer of the hierarchy */
-trait HasConfigurableTLNetworkTopology { this: HasTileLinkLocations =>
+trait HasConfigurableTLNetworkTopology extends LazyModule { this: HasTileLinkLocations with HasPRCILocations =>
   val location: HierarchicalLocation
 
   // Calling these functions populates tlBusWrapperLocationMap and connects the locations to each other.
@@ -93,13 +83,14 @@ abstract class BaseSubsystem(val location: HierarchicalLocation = InSubsystem)
   with HasDTS
   with Attachable
   with HasConfigurablePRCILocations
+  with HasPRCILocations
   with HasConfigurableTLNetworkTopology
 {
   override val module: BaseSubsystemModuleImp[BaseSubsystem]
 
   val busContextName = "subsystem"
 
-  viewpointBus.clockGroupNode := allClockGroupsNode
+  viewpointBus.clockNode := prciClockNode
 
   // TODO: Preserve legacy implicit-clock behavior for IBUS for now. If binding
   //       a PLIC to the CBUS, ensure it is synchronously coupled to the SBUS.

src/main/scala/subsystem/Cluster.scala

@@ -41,14 +41,14 @@ class Cluster(
   lazy val clusterId = thisClusterParams.clusterId
   lazy val location = InCluster(clusterId)
 
-  lazy val allClockGroupsNode = ClockGroupIdentityNode()
+  // lazy val allClockGroupsNode = ClockGroupIdentityNode()
 
   val csbus = tlBusWrapperLocationMap(CSBUS(clusterId)) // like the sbus in the base subsystem
   val ccbus = tlBusWrapperLocationMap(CCBUS(clusterId)) // like the cbus in the base subsystem
   val cmbus = tlBusWrapperLocationMap.lift(CMBUS(clusterId)).getOrElse(csbus)
 
-  csbus.clockGroupNode := allClockGroupsNode
-  ccbus.clockGroupNode := allClockGroupsNode
+  // csbus.clockGroupNode := allClockGroupsNode
+  // ccbus.clockGroupNode := allClockGroupsNode
 
   val slaveNode = ccbus.inwardNode
   val masterNode = cmbus.outwardNode
@@ -169,7 +169,7 @@ trait CanAttachCluster {
 
   def connectPRC(domain: ClusterPRCIDomain, context: ClusterContextType): Unit = {
     implicit val p = context.p
-    domain.element.allClockGroupsNode :*= context.allClockGroupsNode
+    // domain.element.allClockGroupsNode :*= context.allClockGroupsNode
     domain {
       domain.element_reset_domain.clockNode := crossingParams.resetCrossingType.injectClockNode := domain.clockNode
     }

src/main/scala/subsystem/FrontBus.scala

@@ -18,7 +18,7 @@ case class FrontBusParams(
   with HasBuiltInDeviceParams
   with TLBusWrapperInstantiationLike
 {
-  def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): FrontBus = {
+  def instantiate(context: HasTileLinkLocations with HasPRCILocations with LazyModule, loc: Location[TLBusWrapper])(implicit p: Parameters): FrontBus = {
     val fbus = LazyModule(new FrontBus(this, loc.name))
     fbus.suggestName(loc.name)
     context.tlBusWrapperLocationMap += (loc -> fbus)

src/main/scala/subsystem/HasTiles.scala

@@ -278,7 +278,7 @@ trait CanAttachTile {
       case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.clockNode
       case _: AsynchronousCrossing => {
         val tileClockGroup = ClockGroup()
-        tileClockGroup := context.allClockGroupsNode
+        // tileClockGroup := context.allClockGroupsNode
         domain.clockNode := tileClockGroup
       }
     })

src/main/scala/subsystem/MemoryBus.scala

@@ -21,7 +21,7 @@ case class MemoryBusParams(
   with HasRegionReplicatorParams
   with TLBusWrapperInstantiationLike
 {
-  def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): MemoryBus = {
+  def instantiate(context: HasTileLinkLocations with HasPRCILocations with LazyModule, loc: Location[TLBusWrapper])(implicit p: Parameters): MemoryBus = {
     val mbus = LazyModule(new MemoryBus(this, loc.name))
     mbus.suggestName(loc.name)
     context.tlBusWrapperLocationMap += (loc -> mbus)

src/main/scala/subsystem/PeripheryBus.scala

@@ -27,7 +27,7 @@ case class PeripheryBusParams(
   with HasRegionReplicatorParams
   with TLBusWrapperInstantiationLike
 {
-  def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): PeripheryBus = {
+  def instantiate(context: HasTileLinkLocations with HasPRCILocations with LazyModule, loc: Location[TLBusWrapper])(implicit p: Parameters): PeripheryBus = {
     val pbus = LazyModule(new PeripheryBus(this, loc.name))
     pbus.suggestName(loc.name)
     context.tlBusWrapperLocationMap += (loc -> pbus)

src/main/scala/subsystem/SystemBus.scala

@@ -20,7 +20,7 @@ case class SystemBusParams(
   with HasBuiltInDeviceParams
   with TLBusWrapperInstantiationLike
 {
-  def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): SystemBus = {
+  def instantiate(context: HasTileLinkLocations with HasPRCILocations with LazyModule, loc: Location[TLBusWrapper])(implicit p: Parameters): SystemBus = {
     val sbus = LazyModule(new SystemBus(this, loc.name))
     sbus.suggestName(loc.name)
     context.tlBusWrapperLocationMap += (loc -> sbus)

src/main/scala/tilelink/BusWrapper.scala

@@ -36,24 +36,13 @@ abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implici
     with HasTLBusParams
     with CanHaveBuiltInDevices
 {
-  private val clockGroupAggregator = LazyModule(new ClockGroupAggregator(busName){ override def shouldBeInlined = true }).suggestName(busName + "_clock_groups")
-  private val clockGroup = LazyModule(new ClockGroup(busName){ override def shouldBeInlined = true })
-  val clockGroupNode = clockGroupAggregator.node // other bus clock groups attach here
-  val clockNode = clockGroup.node
-  val fixedClockNode = FixedClockBroadcast(fixedClockOpt) // device clocks attach here
+  val clockNode = ClockAdapterNode() // device clocks attach here
+  val fixedClockNode = FixedClockBroadcast(fixedClockOpt)
   private val clockSinkNode = ClockSinkNode(List(ClockSinkParameters(take = fixedClockOpt)))
 
-  clockGroup.node := clockGroupAggregator.node
-  fixedClockNode := clockGroup.node // first member of group is always domain's own clock
+  fixedClockNode := clockNode
   clockSinkNode := fixedClockNode
 
-  InModuleBody {
-    // make sure the above connections work properly because mismatched-by-name signals will just be ignored.
-    (clockGroup.node.edges.in zip clockGroupAggregator.node.edges.out).zipWithIndex map { case ((in: ClockGroupEdgeParameters , out: ClockGroupEdgeParameters), i) =>
-      require(in.members.keys == out.members.keys, s"clockGroup := clockGroupAggregator not working as you expect for index ${i}, becuase clockGroup has ${in.members.keys} and clockGroupAggregator has ${out.members.keys}")
-    }
-  }
-
   def clockBundle = clockSinkNode.in.head._1
   def beatBytes = params.beatBytes
   def blockBytes = params.blockBytes
@@ -94,23 +83,23 @@ abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implici
   def coupleFrom[T](name: String)(gen: TLInwardNode => T): T =
     from(name) { gen(inwardNode :*=* TLNameNode("tl")) }
 
-  def crossToBus(bus: TLBusWrapper, xType: ClockCrossingType, allClockGroupNode: ClockGroupEphemeralNode): NoHandle = {
-    bus.clockGroupNode := asyncMux(xType, allClockGroupNode, this.clockGroupNode)
+  def crossToBus(bus: TLBusWrapper, xType: ClockCrossingType, asyncClockNode: ClockEphemeralNode): NoHandle = {
+    bus.clockNode := asyncMux(xType, asyncClockNode, this.clockNode)
     coupleTo(s"bus_named_${bus.busName}") {
       bus.crossInHelper(xType) :*= TLWidthWidget(beatBytes) :*= _
     }
   }
 
-  def crossFromBus(bus: TLBusWrapper, xType: ClockCrossingType, allClockGroupNode: ClockGroupEphemeralNode): NoHandle = {
-    bus.clockGroupNode := asyncMux(xType, allClockGroupNode, this.clockGroupNode)
+  def crossFromBus(bus: TLBusWrapper, xType: ClockCrossingType, asyncClockNode: ClockEphemeralNode): NoHandle = {
+    this.clockNode := asyncMux(xType, asyncClockNode, bus.clockNode)
     coupleFrom(s"bus_named_${bus.busName}") {
       _ :=* TLWidthWidget(bus.beatBytes) :=* bus.crossOutHelper(xType)
     }
   }
 }
 
 trait TLBusWrapperInstantiationLike {
-  def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): TLBusWrapper
+  def instantiate(context: HasTileLinkLocations with HasPRCILocations with LazyModule, loc: Location[TLBusWrapper])(implicit p: Parameters): TLBusWrapper
 }
 
 trait TLBusWrapperConnectionLike {
@@ -183,8 +172,8 @@ class TLBusWrapperConnection
     val masterTLBus = context.locateTLBusWrapper(master)
     val slaveTLBus  = context.locateTLBusWrapper(slave)
     def bindClocks(implicit p: Parameters) = driveClockFromMaster match {
-      case Some(true)  => slaveTLBus.clockGroupNode  := asyncMux(xType, context.allClockGroupsNode, masterTLBus.clockGroupNode)
-      case Some(false) => masterTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, slaveTLBus.clockGroupNode)
+      case Some(true)  => slaveTLBus.clockNode  := asyncMux(xType, masterTLBus.clockNode, masterTLBus.clockNode)
+      case Some(false) => masterTLBus.clockNode := asyncMux(xType, slaveTLBus.clockNode, slaveTLBus.clockNode)
       case None =>
     }
     def bindTLNodes(implicit p: Parameters) = nodeBinding match {
@@ -214,10 +203,10 @@ class TLBusWrapperTopology(
 ) extends CanInstantiateWithinContextThatHasTileLinkLocations
   with CanConnectWithinContextThatHasTileLinkLocations
 {
-  def instantiate(context: HasTileLinkLocations)(implicit p: Parameters): Unit = {
+  def instantiate(context: HasTileLinkLocations with HasPRCILocations with LazyModule)(implicit p: Parameters): Unit = {
     instantiations.foreach { case (loc, params) => context { params.instantiate(context, loc) } }
   }
-  def connect(context: HasTileLinkLocations)(implicit p: Parameters): Unit = {
+  def connect(context: HasTileLinkLocations with HasPRCILocations with LazyModule)(implicit p: Parameters): Unit = {
     connections.foreach { case (master, slave, params) => context { params.connect(context, master, slave) } }
   }
 }
@@ -244,7 +233,7 @@ case class AddressAdjusterWrapperParams(
   with TLBusWrapperInstantiationLike
 {
   val dtsFrequency = None
-  def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): AddressAdjusterWrapper = {
+  def instantiate(context: HasTileLinkLocations with HasPRCILocations with LazyModule, loc: Location[TLBusWrapper])(implicit p: Parameters): AddressAdjusterWrapper = {
     val aaWrapper = LazyModule(new AddressAdjusterWrapper(this, context.busContextName + "_" + loc.name))
     aaWrapper.suggestName(context.busContextName + "_" + loc.name + "_wrapper")
     context.tlBusWrapperLocationMap += (loc -> aaWrapper)
@@ -274,7 +263,7 @@ case class TLJBarWrapperParams(
   with TLBusWrapperInstantiationLike
 {
   val dtsFrequency = None
-  def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): TLJBarWrapper = {
+  def instantiate(context: HasTileLinkLocations with HasPRCILocations with LazyModule, loc: Location[TLBusWrapper])(implicit p: Parameters): TLJBarWrapper = {
     val jbarWrapper = LazyModule(new TLJBarWrapper(this, context.busContextName + "_" + loc.name))
     jbarWrapper.suggestName(context.busContextName + "_" + loc.name + "_wrapper")
     context.tlBusWrapperLocationMap += (loc -> jbarWrapper)