Add option to use MergedCreditedCrossing in HierarchicalElements

Author: jerryz123

src/main/scala/subsystem/Configs.scala

@@ -12,7 +12,7 @@ import freechips.rocketchip.devices.debug.{DebugModuleKey, DefaultDebugModulePar
 import freechips.rocketchip.devices.tilelink.{
   BuiltInErrorDeviceParams, BootROMLocated, BootROMParams, CLINTKey, DevNullDevice, CLINTParams, PLICKey, PLICParams, DevNullParams
 }
-import freechips.rocketchip.prci.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing, ClockCrossingType}
+import freechips.rocketchip.prci.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing, ClockCrossingType, CreditedCrossing}
 import freechips.rocketchip.diplomacy.{
   AddressSet, MonitorsEnabled,
 }
@@ -517,6 +517,16 @@ class WithRationalRocketTiles extends Config((site, here, up) => {
   }
 })
 
+class WithCreditedRocketTiles(mergedCredited: Boolean = false) extends Config((site, here, up) => {
+  case TilesLocated(location) => up(TilesLocated(location), site) map {
+    case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
+      crossingType = CreditedCrossing(),
+      forceMergedCreditedTLCrossings = mergedCredited
+    ))
+    case t => t
+  }
+})
+
 class WithEdgeDataBits(dataBits: Int) extends Config((site, here, up) => {
   case MemoryBusKey => up(MemoryBusKey, site).copy(beatBytes = dataBits/8)
   case ExtIn => up(ExtIn, site).map(_.copy(beatBytes = dataBits/8))

src/main/scala/subsystem/HierarchicalElement.scala

@@ -35,6 +35,8 @@ trait HierarchicalElementCrossingParamsLike {
   def resetCrossingType: ResetCrossingType
   /** Keep the element clock separate from the interconnect clock (e.g. even if they are synchronous to one another) */
   def forceSeparateClockReset: Boolean
+  /** Used a MergedCreditedTLCrossing for credited TL crossings to save pins */
+  def forceMergedCreditedTLCrossings: Boolean
 }
 
 /** An interface for describing the parameterization of how a particular element port is connected to an interconnect */

src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala

@@ -11,7 +11,7 @@ import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering}
 import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode}
 import freechips.rocketchip.prci.{ClockCrossingType, ResetCrossingType, ResetDomain, ClockSinkNode, ClockSinkParameters, ClockIdentityNode, FixedClockBroadcast, ClockDomain}
 import freechips.rocketchip.tile.{RocketTile, TraceBundle}
-import freechips.rocketchip.tilelink.{TLInwardNode, TLOutwardNode}
+import freechips.rocketchip.tilelink.{TLInwardNode, TLOutwardNode, UseTLMergedCreditedCrossing}
 import freechips.rocketchip.util.TraceCoreInterface
 
 import freechips.rocketchip.tilelink.TLClockDomainCrossing
@@ -83,7 +83,9 @@ abstract class HierarchicalElementPRCIDomain[T <: BaseHierarchicalElement](
         element { element.makeSlaveBoundaryBuffers(crossingType) }
     }
     val tlSlaveClockXing = this.crossIn(tlSlaveResetXing)
-    tlSlaveClockXing(crossingType)
+    tlSlaveClockXing(crossingType)(p.alterPartial {
+      case UseTLMergedCreditedCrossing => crossingParams.forceMergedCreditedTLCrossings
+    })
   } } }
 
   /** External code looking to connect the ports where this tile masters an interconnect
@@ -95,6 +97,8 @@ abstract class HierarchicalElementPRCIDomain[T <: BaseHierarchicalElement](
         element_reset_domain.crossTLOut(element.masterNode)
     } }
     val tlMasterClockXing = this.crossOut(tlMasterResetXing)
-    tlMasterClockXing(crossingType)
+    tlMasterClockXing(crossingType)(p.alterPartial {
+      case UseTLMergedCreditedCrossing => crossingParams.forceMergedCreditedTLCrossings
+    })
   }
 }

src/main/scala/subsystem/RocketSubsystem.scala

@@ -16,7 +16,8 @@ case class RocketCrossingParams(
   slave: HierarchicalElementSlavePortParams = HierarchicalElementSlavePortParams(),
   mmioBaseAddressPrefixWhere: TLBusWrapperLocation = CBUS,
   resetCrossingType: ResetCrossingType = NoResetCrossing(),
-  forceSeparateClockReset: Boolean = false
+  forceSeparateClockReset: Boolean = false,
+  forceMergedCreditedTLCrossings: Boolean = false
 ) extends HierarchicalElementCrossingParamsLike
 
 case class RocketTileAttachParams(