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2 changes: 1 addition & 1 deletion src/main/scala/rocket/ICache.scala
Original file line number Diff line number Diff line change
Expand Up @@ -377,7 +377,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
/** [[io]] access L1 I$ miss. */
val s2_miss = s2_valid && !s2_hit && !io.s2_kill
/** forward signal to stage 1, permit stage 1 refill. */
val s1_can_request_refill = !(s2_miss || refill_valid)
val s1_can_request_refill = !((s2_miss && refill_fire) || refill_valid)
/** real refill signal, stage 2 miss, and was permit to refill in stage 1.
* Since a miss will trigger burst.
* miss under miss won't trigger another burst.
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