TMP HACK [rtl][difftest]: relax AXI max dataWidth to 4096

Author: FanShupei

dependencies/chisel-interface/axi4/src/axi4/bundle/ChiselType.scala

@@ -11,7 +11,7 @@ class AW(val parameter: AXI4BundleParameter) extends AXI4ChiselBundle {
   val id: UInt = UInt(idWidth.W)
   val addr: UInt = UInt(addrWidth.W)
   val len: UInt = UInt(8.W)
-  val size: UInt = UInt(3.W)
+  val size: UInt = UInt(4.W)
   val burst: UInt = UInt(2.W)
   val lock: Bool = Bool()
   val cache: UInt = UInt(4.W)
@@ -39,7 +39,7 @@ class AR(val parameter: AXI4BundleParameter) extends AXI4ChiselBundle {
   val id: UInt = UInt(idWidth.W)
   val addr: UInt = UInt(addrWidth.W)
   val len: UInt = UInt(8.W)
-  val size: UInt = UInt(3.W)
+  val size: UInt = UInt(4.W)
   val burst: UInt = UInt(2.W)
   val lock: Bool = Bool()
   val cache: UInt = UInt(4.W)

dependencies/chisel-interface/axi4/src/axi4/bundle/VerilogType.scala

@@ -43,7 +43,7 @@ trait AWChannel extends AXI4VerilogBundle {
   /** Size, the number of bytes in each data transfer in a write transaction.
     * See IHI0022H A3.4.1
     */
-  val AWSIZE: UInt = UInt(3.W)
+  val AWSIZE: UInt = UInt(4.W)
 
   /** Burst type, indicates how address changes between each transfer in a write
     * transaction.
@@ -147,7 +147,7 @@ trait ARChannel extends AXI4VerilogBundle {
   val ARLEN: UInt = UInt(8.W)
 
   /** Size, the number of bytes in each data transfer in a read transaction. */
-  val ARSIZE: UInt = UInt(3.W)
+  val ARSIZE: UInt = UInt(4.W)
 
   /** Burst type, indicates how address changes between each transfer in a read
     * transaction.

difftest/dpi_t1rocketemu/src/dpi.rs

@@ -132,8 +132,8 @@ unsafe extern "C" fn axi_push_W(
   reset: u8,
   channel_id: u64,
   data_width: u64,
-  wdata: InBV<'_, 1024>,
-  wstrb: InBV<'_, 128>,
+  wdata: InBV<'_, 4096>,
+  wstrb: InBV<'_, 512>,
   wlast: u8,
 
   mut ready: Out<'_, bool>,
@@ -236,7 +236,7 @@ struct RetAxiPopR {
   rlast: u8,
   rid: u16,
   ruser: u32,
-  rdata: [u8; 1024 / 8],
+  rdata: [u8; 4096 / 8],
 }
 
 #[unsafe(no_mangle)]

t1rocketemu/src/AXI4SlaveAgent.scala

@@ -151,8 +151,8 @@ class AXI4SlaveAgent(parameter: AXI4SlaveAgentParameter)
         io.reset.asTypeOf(UInt(8.W)),
         io.channelId,
         parameter.axiParameter.dataWidth.U(64.W),
-        widen(wqueue.io.deq.bits.data, 1024),
-        widen(wqueue.io.deq.bits.strb, 128),
+        widen(wqueue.io.deq.bits.data, 4096),
+        widen(wqueue.io.deq.bits.strb, 512),
         wqueue.io.deq.bits.last.asTypeOf(UInt(8.W))
       )
       wqueue.io.deq.ready := wRet
@@ -204,9 +204,9 @@ class AXI4SlaveAgent(parameter: AXI4SlaveAgentParameter)
       )
       arqueue.io.deq.ready := arRet
 
-      require(parameter.axiParameter.dataWidth <= 1024)
+      require(parameter.axiParameter.dataWidth <= 4096) // Quick fix for DLEN 4096
       class RBundle extends Bundle {
-        val data  = UInt(1024.W)
+        val data  = UInt(4096.W)
         val user  = UInt(32.W)
         val id    = UInt(16.W)
         val last  = UInt(8.W)