[zvma] enable ZVMA on xsfmm* instruction

Signed-off-by: Avimitin <[email protected]>

Author: Avimitin

build.mill

@@ -51,12 +51,13 @@ object t1 extends T1
 trait T1 extends common.T1Module with ScalafmtModule {
   def scalaVersion = T(v.scala)
 
-  def arithmeticIvy    = v.arithmetic
-  def axi4Ivy          = v.axi4
-  def hardfloatIvy     = v.hardfloat
-  def rvdecoderdbIvy   = v.rvdecoderdb
-  def stdlibModule     = stdlib
-  def riscvOpcodesPath = T.input(PathRef(millSourcePath / os.up / "dependencies" / "riscv-opcodes"))
+  def arithmeticIvy          = v.arithmetic
+  def axi4Ivy                = v.axi4
+  def hardfloatIvy           = v.hardfloat
+  def rvdecoderdbIvy         = v.rvdecoderdb
+  def stdlibModule           = stdlib
+  def riscvOpcodesPath       = T.input(PathRef(millSourcePath / os.up / "dependencies" / "riscv-opcodes"))
+  def riscvCustomOpcodesPath = T.input(PathRef(millSourcePath / os.up / "custom-instructions"))
 
   def chiselModule    = None
   def chiselPluginJar = None
@@ -77,12 +78,13 @@ trait ConfigGen extends common.ConfigGenModule with ScalafmtModule {
 object rocketv extends RocketV
 
 trait RocketV extends common.RocketVModule with ScalafmtModule {
-  def scalaVersion     = T(v.scala)
-  def rvdecoderdbIvy   = v.rvdecoderdb
-  def riscvOpcodesPath = T.input(PathRef(millSourcePath / os.up / "dependencies" / "riscv-opcodes"))
-  def hardfloatIvy     = v.hardfloat
-  def axi4Ivy          = v.axi4
-  def stdlibModule     = stdlib
+  def scalaVersion           = T(v.scala)
+  def rvdecoderdbIvy         = v.rvdecoderdb
+  def riscvOpcodesPath       = T.input(PathRef(millSourcePath / os.up / "dependencies" / "riscv-opcodes"))
+  def riscvCustomOpcodesPath = T.input(PathRef(millSourcePath / os.up / "custom-instructions"))
+  def hardfloatIvy           = v.hardfloat
+  def axi4Ivy                = v.axi4
+  def stdlibModule           = stdlib
 
   def chiselModule    = None
   def chiselPluginJar = None

common.mill

@@ -33,10 +33,11 @@ trait HasChisel extends ScalaModule {
 }
 
 trait HasRVDecoderDB extends ScalaModule {
-  def rvdecoderdbIvy:   Dep
-  def riscvOpcodesPath: T[PathRef]
+  def rvdecoderdbIvy:         Dep
+  def riscvOpcodesPath:       T[PathRef]
+  def riscvCustomOpcodesPath: T[PathRef]
   def ivyDeps = T(super.ivyDeps() ++ Seq(rvdecoderdbIvy))
-  def riscvOpcodesTar:    T[PathRef]      = T {
+  def riscvOpcodesTar:       T[PathRef] = T {
     val tmpDir = os.temp.dir()
     os.makeDir(tmpDir / "unratified")
     os.walk(riscvOpcodesPath().path)
@@ -55,7 +56,21 @@ trait HasRVDecoderDB extends ScalaModule {
     os.proc("tar", "cf", T.dest / "riscv-opcodes.tar", ".").call(tmpDir)
     PathRef(T.dest)
   }
-  override def resources: T[Seq[PathRef]] = super.resources() ++ Some(riscvOpcodesTar())
+  def riscvCustomOpcodesTar: T[PathRef] = T {
+    val tmpDir = os.temp.dir()
+    os.walk(riscvCustomOpcodesPath().path)
+      .filter(f =>
+        f.baseName.startsWith("rv128_") ||
+          f.baseName.startsWith("rv64_") ||
+          f.baseName.startsWith("rv32_") ||
+          f.baseName.startsWith("rv_")
+      )
+      .foreach(os.copy.into(_, tmpDir))
+    os.proc("tar", "cf", T.dest / "riscv-custom-opcodes.tar", ".").call(tmpDir)
+    PathRef(T.dest)
+  }
+
+  override def resources: T[Seq[PathRef]] = super.resources() ++ Seq(riscvOpcodesTar(), riscvCustomOpcodesTar())
 }
 
 // Local definitions
@@ -75,12 +90,6 @@ trait ConfigGenModule extends ScalaModule {
   override def ivyDeps = T(super.ivyDeps() ++ Seq(mainargsIvy))
 }
 
-// T1 forked version of RocketCore
-trait RocketModule extends ScalaModule with HasChisel with HasRVDecoderDB {
-  def rocketchipModule: ScalaModule
-  def moduleDeps = super.moduleDeps ++ Seq(rocketchipModule)
-}
-
 // The next generation of purely standalone Rocket Core w/ AXI/CHI.
 trait RocketVModule extends ScalaModule with HasChisel with HasRVDecoderDB {
   def axi4Ivy:      Dep

custom-instructions/rv_xsfmm

@@ -0,0 +1,25 @@
+# TODO: wait for arg_lut upstream for mtile: https://github.com/riscv/riscv-opcodes/pull/340
+vsettn       31=1 30..25=0x02 24..20=0x00 rs1 14..12=7 rd 6..0=0x57
+vsettm       31=1 30..25=0x02 24..20=0x01 rs1 14..12=7 rd 6..0=0x57
+vsettk       31=1 30..25=0x02 24..20=0x02 rs1 14..12=7 rd 6..0=0x57
+vlte8        31..29=0 28=1 27=0 26=0 25=1 rs2 rs1 14..12=7 11..7=0 6..0=0x07
+vlte16       31..29=1 28=1 27=0 26=0 25=1 rs2 rs1 14..12=7 11..7=0 6..0=0x07
+vlte32       31..29=2 28=1 27=0 26=0 25=1 rs2 rs1 14..12=7 11..7=0 6..0=0x07
+vlte64       31..29=3 28=1 27=0 26=0 25=1 rs2 rs1 14..12=7 11..7=0 6..0=0x07
+vste8        31..29=0 28=1 27=0 26=0 25=1 rs2 rs1 14..12=7 11..7=0 6..0=0x27
+vste16       31..29=1 28=1 27=0 26=0 25=1 rs2 rs1 14..12=7 11..7=0 6..0=0x27
+vste32       31..29=2 28=1 27=0 26=0 25=1 rs2 rs1 14..12=7 11..7=0 6..0=0x27
+vste64       31..29=3 28=1 27=0 26=0 25=1 rs2 rs1 14..12=7 11..7=0 6..0=0x27
+vtmv.v.t     31..26=0x10 25=1 24..20=0x1F rs1 14..12=6 vd 6..0=0x57
+vtmv.t.v     31..26=0x17 25=1 vs2 rs1 14..12=6 11..7=0x00 6..0=0x57
+mm.e5m2.e5m2 31..26=0x3E 25=1 vs2 vs1 14..12=1 9=0 8=0 7=0 6..0=0x77
+mm.e5m2.e4m3 31..26=0x3E 25=1 vs2 vs1 14..12=1 9=0 8=0 7=1 6..0=0x77
+mm.e4m3.e5m2 31..26=0x3F 25=1 vs2 vs1 14..12=1 9=0 8=0 7=0 6..0=0x77
+mm.e4m3.e4m3 31..26=0x3F 25=1 vs2 vs1 14..12=1 9=0 8=0 7=1 6..0=0x77
+mm.u.u       31..26=0x3C 25=1 vs2 vs1 14..12=0 9=0 8=0 7=0 6..0=0x77
+mm.s.u       31..26=0x3D 25=1 vs2 vs1 14..12=0 9=0 8=0 7=0 6..0=0x77
+mm.u.s       31..26=0x3C 25=1 vs2 vs1 14..12=0 9=0 8=0 7=1 6..0=0x77
+mm.s.s       31..26=0x3D 25=1 vs2 vs1 14..12=0 9=0 8=0 7=1 6..0=0x77
+p2mm.f.f     31..26=0x3C 25=1 vs2 vs1 14..12=1 8=0 7=1 6..0=0x77
+vtzero.t     31..26=0x10 25=1 24..20=0x1E 19..15=0x00 14..12=6 7=0 6..0=0x57
+vtdiscard    31..26=0x10 25=1 24..20=0x1C 19..15=0x00 14..12=6 11..7=0x00 6..0=0x57