column_limit affects the formatting even when we are under the limit

[furkanu-work]

Test case

class foo;
    bit some_very_very_very_long_variable;
    bit     some_other_variable [bit[80:0]];
endclass

In the input the widest line is at 44 characters

Actual output

verible-verilog-format --column_limit 49 foo.sv

class foo;
  bit some_very_very_very_long_variable;
  bit some_other_variable[bit            [80:0]];
endclass

Expected or suggested output

verible-verilog-format --column_limit 48 foo.sv

class foo;
  bit some_very_very_very_long_variable;
  bit some_other_variable[bit [80:0]];
endclass

I'd expect both to be the same

Version

Version v0.0-4051-g9fdb4057
Commit-Timestamp        2025-12-22T08:55:10Z
Built   2025-12-22T08:59:31Z