Formatter failure with long line with macros #2492
Description
Test case
Minimum reproducible test case
$ verible-verilog-format --flagfile=.rules.verible_format test.svclass dut_sc_checker extends sc_uvc_checker;
`uvm_component_utils(dut_sc_checker)
function new(string name = "dut_sc_checker", uvm_component parent);
super.new(name, parent);
endfunction
function bit check_status(sc_uvc_sequence_item req);
bit error = 1'b0;
error |= condition(!req.m_status[ERR_SINGLECHIP_BYPASS], "SC_STS_NOTTODUT_NO_ERR_SINGLECHIP_BYPASS", $sformatf("Status bit is not set for transaction not directed to DUT\n%s", req.sprint()), `uvm_file, `uvm_line);
return error;
endfunction
endclassInclude any options or configuration used.
$ cat .rules.verible_format
--failsafe_success=false
--inplace
--line_break_penalty=8
--column_limit=200
--over_column_limit_penalty=100
--named_port_alignment=flush-left
Actual output of the command
$ verible-verilog-format --flagfile=.rules.verible_format test.sv
test.sv: Formatted output is lexically different from the input. Please file a bug. Details:
Mismatched token enums. got: (MacroIdentifier) (#296: "`uvm_line") vs. (MacroIdItem) (#298: "`uvm_line")
First mismatched token [73]: (MacroIdentifier) (#296: "`uvm_line") vs. (MacroIdItem) (#298: "`uvm_line")
; problematic formatter output is
class dut_sc_checker extends sc_uvc_checker;
`uvm_component_utils(dut_sc_checker)
function new(string name = "dut_sc_checker", uvm_component parent);
super.new(name, parent);
endfunction
function bit check_status(sc_uvc_sequence_item req);
bit error = 1'b0;
error |= condition(
!req.m_status[ERR_SINGLECHIP_BYPASS], "SC_STS_NOTTODUT_NO_ERR_SINGLECHIP_BYPASS", $sformatf("Status bit is not set for transaction not directed to DUT\n%s", req.sprint()), `uvm_file, `uvm_line
);
return error;
endfunction
endclass
<<EOF>>Include any possible diagnostic messages from the formatter.
- The line which is problematic seems to be this one, shortening it, results in the formatter passing.
error |= condition(!req.m_status[ERR_SINGLECHIP_BYPASS], "SC_STS_NOTTODUT_NO_ERR_SINGLECHIP_BYPASS", $sformatf("Status bit is not set for transaction not directed to DUT\n%s", req.sprint()), `uvm_file, `uvm_line);- verible versions affected
$ verible-verilog-format -version
Version v0.0-4051-g9fdb4057
Commit-Timestamp 2025-12-22T08:55:10Z
Built 2025-12-22T08:59:31Zand
$ verible-verilog-format -version
Version v0.0-4023-gc1271a00
Commit-Timestamp 2025-08-29T09:25:59Z
Built 2025-08-29T09:28:29Z- In previous issues of this kind, users were asked to produce a syntax tree dump
Parse Tree:
Node @0 (tag: kDescriptionList) {
Node @0 (tag: kClassDeclaration) {
Node @0 (tag: kClassHeader) {
Leaf @1 (#"class" @0-5: "class")
Leaf @3 (#SymbolIdentifier @6-20: "dut_sc_checker")
Node @5 (tag: kExtendsList) {
Leaf @0 (#"extends" @21-28: "extends")
Node @1 (tag: kUnqualifiedId) {
Leaf @0 (#SymbolIdentifier @29-43: "sc_uvc_checker")
}
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Leaf @7 (#';' @43-44: ";")
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Node @1 (tag: kClassItems) {
Node @0 (tag: kMacroCall) {
Leaf @0 (#MacroCallId @47-67: "`uvm_component_utils")
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Leaf @0 (#SymbolIdentifier @68-82: "dut_sc_checker")
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Leaf @3 (#';' @152-153: ";")
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Leaf @0 (#"bit" @208-211: "bit")
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Node @3 (tag: kPackedDimensions) {
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Node @4 (tag: kUnqualifiedId) {
Leaf @0 (#SymbolIdentifier @212-224: "check_status")
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Leaf @0 (#'(' @224-225: "(")
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Node @3 (tag: kPackedDimensions) {
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Node @1 (tag: kUnpackedDimensions) {
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Leaf @0 (#'=' @266-267: "=")
Node @1 (tag: kExpression) {
Node @0 (tag: kNumber) {
Leaf @0 (#TK_DecNumber @268-269: "1")
Node @1 (tag: kBaseDigits) {
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Leaf @1 (#TK_BinDigits @271-272: "0")
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Leaf @2 (#';' @272-273: ";")
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Leaf @1 (#"|=" @284-286: "|=")
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Leaf @0 (#SymbolIdentifier @298-301: "req")
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Leaf @0 (#'.' @301-302: ".")
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Leaf @0 (#SymbolIdentifier @302-310: "m_status")
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Leaf @2 (#']' @332-333: "]")
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}
Leaf @1 (#',' @333-334: ",")
Node @2 (tag: kExpression) {
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Leaf @3 (#',' @377-378: ",")
Node @4 (tag: kExpression) {
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Leaf @1 (#',' @452-453: ",")
Node @2 (tag: kExpression) {
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Node @0 (tag: kReferenceCallBase) {
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Leaf @0 (#SymbolIdentifier @454-457: "req")
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Leaf @0 (#SymbolIdentifier @458-464: "sprint")
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Leaf @0 (#'(' @464-465: "(")
Leaf @2 (#')' @465-466: ")")
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Leaf @2 (#')' @466-467: ")")
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}
Leaf @5 (#',' @467-468: ",")
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Leaf @2 (#')' @489-490: ")")
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Leaf @3 (#';' @490-491: ";")
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Leaf @3 (#"endfunction" @512-523: "endfunction")
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