wip

Author: wsipak

systemverilog-plugin/UhdmAst.cc

@@ -1282,6 +1282,10 @@ static void simplify_sv(AST::AstNode *current_node, AST::AstNode *parent_node)
         if (current_node->str == "$display" || current_node->str == "$write")
             simplify_format_string(current_node);
         break;
+    case AST::AST_FCALL:
+        while (simplify(current_node, true, false, false, 1, -1, false, false)) {
+        };
+        break;
     case AST::AST_COND:
     case AST::AST_CONDX:
     case AST::AST_CONDZ:

systemverilog-plugin/third_party/yosys/simplify.cc

@@ -54,7 +54,6 @@ using namespace ::Yosys::AST_INTERNAL;
 
 void detect_sign_width_proxy(Yosys::AST::AstNode * node, int& width, bool& sign, bool *found_real = NULL) {
     if (node->type == Yosys::AST::AST_IDENTIFIER && node->id2ast && node->id2ast->type == Yosys::AST::AST_TYPEDEF) {
-        node->id2ast->dumpAst(nullptr, "---------");
         node->id2ast = node->id2ast->children[0];
     }
     node->detectSignWidth(width, sign, found_real);