Add separate-compilation test

Signed-off-by: Rafal Kapuscik <[email protected]>

Author: Rafal Kapuscik

systemverilog-plugin/tests/Makefile

@@ -14,9 +14,12 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-TESTS = counter break_continue
+TESTS = counter \
+		break_continue \
+		separate-compilation
 
 include $(shell pwd)/../../Makefile_test.common
 
 counter_verify = true
 break_continue_verify = $(call diff_test,break_continue,out)
+separate-compilation_verify = true

systemverilog-plugin/tests/separate-compilation/separate-compilation-buf.sv

@@ -0,0 +1,21 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module BUF (
+  input I,
+  output O
+);
+  assign O = I;
+endmodule;

systemverilog-plugin/tests/separate-compilation/separate-compilation-pkg.sv

@@ -0,0 +1,19 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+package pkg;
+  parameter BITS = 4;
+  parameter LOG2DELAY = 22;
+endpackage

systemverilog-plugin/tests/separate-compilation/separate-compilation.tcl

@@ -0,0 +1,16 @@
+yosys -import
+if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
+yosys -import  ;# ingest plugin commands
+
+set TMP_DIR /tmp
+if { [info exists ::env(TMPDIR) ] } {
+  set TMP_DIR $::env(TMPDIR)
+}
+
+# Testing simple round-trip
+read_systemverilog -odir $TMP_DIR/separate-compilation-test -defer $::env(DESIGN_TOP)-pkg.sv
+read_systemverilog -odir $TMP_DIR/separate-compilation-test -defer $::env(DESIGN_TOP)-buf.sv
+read_systemverilog -odir $TMP_DIR/separate-compilation-test -defer $::env(DESIGN_TOP).v
+read_systemverilog -odir $TMP_DIR/separate-compilation-test -link
+hierarchy
+write_verilog

systemverilog-plugin/tests/separate-compilation/separate-compilation.v

@@ -0,0 +1,31 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module top (
+  input clk,
+  output [3:0] led
+);
+
+  wire bufg;
+  BUF bufgctrl (
+      .I(clk),
+      .O(bufg)
+  );
+  reg [pkg::BITS + pkg::LOG2DELAY-1 : 0] counter = 0;
+  always @(posedge bufg) begin
+    counter <= counter + 1;
+  end
+  assign led[3:0] = counter >> pkg::LOG2DELAY;
+endmodule