Add support for variables defined inside named blocks

Signed-off-by: Kamil Rakoczy <[email protected]>

Author: kamilrakoczy

uhdm-plugin/UhdmAst.cc

@@ -2049,11 +2049,13 @@ void UhdmAst::process_begin()
     });
     // TODO: find out how to set VERILOG_FRONTEND::sv_mode to true
     // simplify checks if sv_mode is set to ture when wire is declared inside unnamed block
-    /*visit_one_to_many({vpiVariables}, obj_h, [&](AST::AstNode *node) {
-        if (node) {
-            current_node->children.push_back(node);
-        }
-    });*/
+    if (!current_node->str.empty()) {
+        visit_one_to_many({vpiVariables}, obj_h, [&](AST::AstNode *node) {
+            if (node) {
+                current_node->children.push_back(node);
+            }
+        });
+    }
 }
 
 void UhdmAst::process_operation()