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Initial checkin for arith-stats plugin.
Signed-off-by: Tim Callahan <[email protected]>
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Makefile

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#
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# SPDX-License-Identifier: Apache-2.0
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PLUGIN_LIST := fasm xdc params sdc ql-iob design_introspection integrateinv ql-qlf systemverilog uhdm dsp-ff
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PLUGIN_LIST := fasm xdc params sdc ql-iob design_introspection \
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integrateinv ql-qlf systemverilog uhdm dsp-ff arith-stats
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PLUGINS := $(foreach plugin,$(PLUGIN_LIST),$(plugin).so)
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PLUGINS_INSTALL := $(foreach plugin,$(PLUGIN_LIST),install_$(plugin))
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PLUGINS_CLEAN := $(foreach plugin,$(PLUGIN_LIST),clean_$(plugin))

arith-stats-plugin/Makefile

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# Copyright 2020-2022 F4PGA Authors
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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CXXFLAGS := -std=c++17
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NAME = arith-stats
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SOURCES = arith-stats.cc
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include ../Makefile_plugin.common

arith-stats-plugin/arith-stats.cc

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#include <stdlib.h>
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#include <algorithm>
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#include <string>
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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#include "kernel/yosys.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct ArithStats : public Pass {
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ArithStats()
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: Pass("arith_stats",
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"Print out information about arithmetic operators in design.") {}
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void help() override {
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" arith_stats\n");
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log("\n");
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log("Print out information about arithmetic operators in design.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override {
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(void)args; // no args / not used
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log("Executing 'arith_stats' command.");
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for (const RTLIL::Module *module : design->selected_modules()) {
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std::map<RTLIL::IdString, std::map<int, int>> histos_by_type;
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std::map<RTLIL::IdString, int> tot_counts;
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// === COLLECT data for this module
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for (const RTLIL::Cell *cell : module->selected_cells()) {
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if (!cell->type.in(ID($add), ID($sub), ID($neg), ID($alu), ID($fa),
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ID($macc), ID($mul), ID($div), ID($lt), ID($le),
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ID($gt), ID($ge))) {
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continue;
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}
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// Get the width of the arith cell
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int width = 0;
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if (cell->type.in(ID($fa))) {
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width = std::max(width, cell->parameters.at(ID::WIDTH).as_int());
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} else {
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width = std::max(width, cell->parameters.at(ID::A_WIDTH).as_int());
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if (!cell->type.in(ID($neg))) {
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width = std::max(width, cell->parameters.at(ID::B_WIDTH).as_int());
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}
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width = std::max(width, cell->parameters.at(ID::Y_WIDTH).as_int());
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}
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// update total counts by type
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const auto typ = cell->type;
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tot_counts[typ] = (tot_counts.count(typ) ? tot_counts[typ] : 0) + 1;
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// update width historgram
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auto &histo = histos_by_type[typ];
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histo[width] = (histo.count(width) ? histo[width] : 0) + 1;
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}
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// === DISPLAY info for this module
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if (!histos_by_type.empty()) {
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log("\nCounting arithmetic cells in module %s:\n",
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module->name.c_str());
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}
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for (const auto &[typ, histo] : histos_by_type) {
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log("\n%s: total %d instances\n", typ.c_str(), tot_counts[typ]);
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log(" %10s : %-10s\n", "bitwidth", "count");
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for (const auto &[width, count] : histo) {
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log(" %10d : %-10d\n", width, count);
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}
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}
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}
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}
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};
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static struct ArithStats *instance = new struct ArithStats();
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PRIVATE_NAMESPACE_END

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