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| 1 | +#include <stdlib.h> |
| 2 | + |
| 3 | +#include <algorithm> |
| 4 | +#include <string> |
| 5 | + |
| 6 | +#include "kernel/celltypes.h" |
| 7 | +#include "kernel/log.h" |
| 8 | +#include "kernel/register.h" |
| 9 | +#include "kernel/rtlil.h" |
| 10 | +#include "kernel/sigtools.h" |
| 11 | +#include "kernel/yosys.h" |
| 12 | + |
| 13 | +USING_YOSYS_NAMESPACE |
| 14 | +PRIVATE_NAMESPACE_BEGIN |
| 15 | + |
| 16 | +struct ArithStats : public Pass { |
| 17 | + ArithStats() |
| 18 | + : Pass("arith_stats", |
| 19 | + "Print out information about arithmetic operators in design.") {} |
| 20 | + |
| 21 | + void help() override { |
| 22 | + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| |
| 23 | + log("\n"); |
| 24 | + log(" arith_stats\n"); |
| 25 | + log("\n"); |
| 26 | + log("Print out information about arithmetic operators in design.\n"); |
| 27 | + log("\n"); |
| 28 | + } |
| 29 | + |
| 30 | + void execute(std::vector<std::string> args, RTLIL::Design *design) override { |
| 31 | + (void)args; // no args / not used |
| 32 | + log("Executing 'arith_stats' command."); |
| 33 | + for (const RTLIL::Module *module : design->selected_modules()) { |
| 34 | + std::map<RTLIL::IdString, std::map<int, int>> histos_by_type; |
| 35 | + std::map<RTLIL::IdString, int> tot_counts; |
| 36 | + |
| 37 | + // === COLLECT data for this module |
| 38 | + for (const RTLIL::Cell *cell : module->selected_cells()) { |
| 39 | + if (!cell->type.in(ID($add), ID($sub), ID($neg), ID($alu), ID($fa), |
| 40 | + ID($macc), ID($mul), ID($div), ID($lt), ID($le), |
| 41 | + ID($gt), ID($ge))) { |
| 42 | + continue; |
| 43 | + } |
| 44 | + |
| 45 | + // Get the width of the arith cell |
| 46 | + int width = 0; |
| 47 | + if (cell->type.in(ID($fa))) { |
| 48 | + width = std::max(width, cell->parameters.at(ID::WIDTH).as_int()); |
| 49 | + } else { |
| 50 | + width = std::max(width, cell->parameters.at(ID::A_WIDTH).as_int()); |
| 51 | + if (!cell->type.in(ID($neg))) { |
| 52 | + width = std::max(width, cell->parameters.at(ID::B_WIDTH).as_int()); |
| 53 | + } |
| 54 | + width = std::max(width, cell->parameters.at(ID::Y_WIDTH).as_int()); |
| 55 | + } |
| 56 | + |
| 57 | + // update total counts by type |
| 58 | + const auto typ = cell->type; |
| 59 | + tot_counts[typ] = (tot_counts.count(typ) ? tot_counts[typ] : 0) + 1; |
| 60 | + |
| 61 | + // update width historgram |
| 62 | + auto &histo = histos_by_type[typ]; |
| 63 | + histo[width] = (histo.count(width) ? histo[width] : 0) + 1; |
| 64 | + } |
| 65 | + |
| 66 | + // === DISPLAY info for this module |
| 67 | + if (!histos_by_type.empty()) { |
| 68 | + log("\nCounting arithmetic cells in module %s:\n", |
| 69 | + module->name.c_str()); |
| 70 | + } |
| 71 | + for (const auto &[typ, histo] : histos_by_type) { |
| 72 | + log("\n%s: total %d instances\n", typ.c_str(), tot_counts[typ]); |
| 73 | + log(" %10s : %-10s\n", "bitwidth", "count"); |
| 74 | + for (const auto &[width, count] : histo) { |
| 75 | + log(" %10d : %-10d\n", width, count); |
| 76 | + } |
| 77 | + } |
| 78 | + } |
| 79 | + } |
| 80 | +}; |
| 81 | + |
| 82 | +static struct ArithStats *instance = new struct ArithStats(); |
| 83 | + |
| 84 | +PRIVATE_NAMESPACE_END |
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