rename synth_quicklogic to synth_quicklogic_f4pga to not conflict with yosys internal

Author: timkpaine

.github/workflows/ci.yml

@@ -70,7 +70,7 @@ jobs:
     - name: Install Mac Dependencies
       run: |
         brew update
-        brew install make cmake graphviz bison flex boost nlohmann-json yosys icarus-verilog
+        brew install make cmake graphviz bison flex boost nlohmann-json icarus-verilog
         sudo ln -s /usr/local/bin/gmake /usr/local/bin/make
       if: ${{ runner.os == 'macOS'}}
 
@@ -92,7 +92,6 @@ jobs:
           git clone --branch yosys-0.17 https://github.com/YosysHQ/yosys.git
           pushd yosys
           make -j`nproc` && sudo make install
-      if: ${{ runner.os != 'macOS'}}
 
     - name: Install Googletest
       run: |

README.md

@@ -82,7 +82,7 @@ The plugin adds the following command:
 
 The plugin adds the following command:
 
-* synth_quicklogic
+* synth_quicklogic_f4pga
 * ql_dsp
 
 Detailed help on the supported command(s) can be obtained by running `help <command_name>` in Yosys.

ql-qlf-plugin/qlf_k6n10/ffs_map.v

@@ -97,7 +97,7 @@ module  \$_DLATCHSR_PPP_ (input E, S, R, D, output Q);
 endmodule
 
 // The following techmap operation are not performed right now
-// as Negative edge FF are not legalized in synth_quicklogic for qlf_k6n10
+// as Negative edge FF are not legalized in synth_quicklogic_f4pga for qlf_k6n10
 // but in case we implement clock inversion in the future, the support is ready for it.
 
 module \$_DFF_N_ (D, C, Q);

ql-qlf-plugin/synth_quicklogic.cc

@@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
 #define STR(val) XSTR(val)
 
 #ifndef PASS_NAME
-#define PASS_NAME synth_quicklogic
+#define PASS_NAME synth_quicklogic_f4pga
 #endif
 
 struct SynthQuickLogicPass : public ScriptPass {
@@ -230,7 +230,7 @@ struct SynthQuickLogicPass : public ScriptPass {
             design->scratchpad_set_int("abc9.D", 41667); // 12MHz = 83.33.. ns; divided by two to allow for interconnect delay.
         }
 
-        log_header(design, "Executing SYNTH_QUICKLOGIC pass.\n");
+        log_header(design, "Executing synth_quicklogic_f4pga pass.\n");
         log_push();
 
         run_script(design, run_from, run_to);

ql-qlf-plugin/tests/consts/consts.tcl

@@ -4,7 +4,7 @@ yosys -import  ;# ingest plugin commands
 
 read_verilog $::env(DESIGN_TOP).v
 
-synth_quicklogic -top my_top -family pp3
+synth_quicklogic_f4pga -top my_top -family pp3
 stat
 yosys cd my_top
 select -assert-count 1 t:my_lut