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timkpainetimkpaine
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Rename synth_quicklogic to synth_quicklogic_f4pga to not conflict with yosys builtin
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‎README.md‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ The plugin adds the following command:
5757

5858
The plugin adds the following command:
5959

60-
* synth_quicklogic
60+
* synth_quicklogic_f4pga
6161
* ql_dsp
6262

6363
Detailed help on the supported command(s) can be obtained by running `help <command_name>` in Yosys.

‎ql-qlf-plugin/Makefile‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -108,6 +108,6 @@ $(PMGEN_OUT_DIR)/ql-bram-asymmetric-wider-read.h: ql-bram-asymmetric-wider-read.
108108
python3 $(PMGEN_PY) -o $@ -p ql_bram_asymmetric_wider_read ql-bram-asymmetric-wider-read.pmg
109109

110110
install_modules: $(VERILOG_MODULES)
111-
$(foreach f,$^,install -D $(f) $(YOSYS_DATA_DIR)/quicklogic/$(f);)
111+
$(foreach f,$^,install -D $(f) $(YOSYS_DATA_DIR)/quicklogic_f4pga/$(f);)
112112

113113
install: install_modules

‎ql-qlf-plugin/synth_quicklogic.cc‎

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
2828
#define STR(val) XSTR(val)
2929

3030
#ifndef PASS_NAME
31-
#define PASS_NAME synth_quicklogic
31+
#define PASS_NAME synth_quicklogic_f4pga
3232
#endif
3333

3434
struct SynthQuickLogicPass : public ScriptPass {
@@ -241,7 +241,7 @@ struct SynthQuickLogicPass : public ScriptPass {
241241
void script() override
242242
{
243243
if (check_label("begin")) {
244-
std::string family_path = " +/quicklogic/" + family;
244+
std::string family_path = " +/quicklogic_f4pga/" + family;
245245
std::string readVelArgs;
246246

247247
// Read simulation library
@@ -254,7 +254,7 @@ struct SynthQuickLogicPass : public ScriptPass {
254254
// Use -nomem2reg here to prevent Yosys from complaining about
255255
// some block ram cell models. After all the only part of the cells
256256
// library required here is cell port definitions plus specify blocks.
257-
run("read_verilog -lib -specify -nomem2reg +/quicklogic/common/cells_sim.v" + readVelArgs);
257+
run("read_verilog -lib -specify -nomem2reg +/quicklogic_f4pga/common/cells_sim.v" + readVelArgs);
258258
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
259259
}
260260

@@ -291,7 +291,7 @@ struct SynthQuickLogicPass : public ScriptPass {
291291
if (help_mode || !nodsp) {
292292
run("memory_dff");
293293
run("wreduce t:$mul");
294-
run("techmap -map +/mul2dsp.v -map +/quicklogic/" + family +
294+
run("techmap -map +/mul2dsp.v -map +/quicklogic_f4pga/" + family +
295295
"/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
296296
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
297297
"-D DSP_NAME=$__MUL16X16",
@@ -324,13 +324,13 @@ struct SynthQuickLogicPass : public ScriptPass {
324324
run("ql_dsp_macc" + use_dsp_cfg_params, "(for qlf_k6n10f if not -no_dsp)");
325325
run("techmap -map +/mul2dsp.v [...]", " (for qlf_k6n10f if not -no_dsp)");
326326
run("chtype -set $mul t:$__soft_mul", " (for qlf_k6n10f if not -no_dsp)");
327-
run("techmap -map +/quicklogic/" + family + "/dsp_map.v", "(for qlf_k6n10f if not -no_dsp)");
327+
run("techmap -map +/quicklogic_f4pga/" + family + "/dsp_map.v", "(for qlf_k6n10f if not -no_dsp)");
328328
if (use_dsp_cfg_params.empty())
329-
run("techmap -map +/quicklogic/" + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0", "(for qlf_k6n10f if not -no_dsp)");
329+
run("techmap -map +/quicklogic_f4pga/" + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0", "(for qlf_k6n10f if not -no_dsp)");
330330
else
331-
run("techmap -map +/quicklogic/" + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=1", "(for qlf_k6n10f if not -no_dsp)");
331+
run("techmap -map +/quicklogic_f4pga/" + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=1", "(for qlf_k6n10f if not -no_dsp)");
332332
run("ql_dsp_simd ", "(for qlf_k6n10f if not -no_dsp)");
333-
run("techmap -map +/quicklogic/" + family + "/dsp_final_map.v", "(for qlf_k6n10f if not -no_dsp)");
333+
run("techmap -map +/quicklogic_f4pga/" + family + "/dsp_final_map.v", "(for qlf_k6n10f if not -no_dsp)");
334334
run("ql_dsp_io_regs");
335335
} else if (!nodsp) {
336336

@@ -346,11 +346,11 @@ struct SynthQuickLogicPass : public ScriptPass {
346346
run("chtype -set $mul t:$__soft_mul");
347347
}
348348
if (use_dsp_cfg_params.empty())
349-
run("techmap -map +/quicklogic/" + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0");
349+
run("techmap -map +/quicklogic_f4pga/" + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0");
350350
else
351-
run("techmap -map +/quicklogic/" + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=1");
351+
run("techmap -map +/quicklogic_f4pga/" + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=1");
352352
run("ql_dsp_simd");
353-
run("techmap -map +/quicklogic/" + family + "/dsp_final_map.v");
353+
run("techmap -map +/quicklogic_f4pga/" + family + "/dsp_final_map.v");
354354
run("ql_dsp_io_regs");
355355
}
356356
}
@@ -370,14 +370,14 @@ struct SynthQuickLogicPass : public ScriptPass {
370370
}
371371

372372
if (check_label("map_bram", "(skip if -no_bram)") && (family == "qlf_k6n10" || family == "qlf_k6n10f" || family == "pp3") && inferBram) {
373-
run("memory_bram -rules +/quicklogic/" + family + "/brams.txt");
373+
run("memory_bram -rules +/quicklogic_f4pga/" + family + "/brams.txt");
374374
if (family == "pp3") {
375375
run("pp3_braminit");
376376
}
377377
run("ql_bram_split ", "(for qlf_k6n10f if not -no_bram)");
378-
run("techmap -autoproc -map +/quicklogic/" + family + "/brams_map.v");
378+
run("techmap -autoproc -map +/quicklogic_f4pga/" + family + "/brams_map.v");
379379
if (family == "qlf_k6n10f") {
380-
run("techmap -map +/quicklogic/" + family + "/brams_final_map.v");
380+
run("techmap -map +/quicklogic_f4pga/" + family + "/brams_final_map.v");
381381
}
382382

383383
// Data width to specialized cell type width map
@@ -439,7 +439,7 @@ struct SynthQuickLogicPass : public ScriptPass {
439439

440440
if (check_label("map_gates")) {
441441
if (inferAdder && (family == "qlf_k4n8" || family == "qlf_k6n10" || family == "qlf_k6n10f")) {
442-
run("techmap -map +/techmap.v -map +/quicklogic/" + family + "/arith_map.v");
442+
run("techmap -map +/techmap.v -map +/quicklogic_f4pga/" + family + "/arith_map.v");
443443
} else {
444444
run("techmap");
445445
}
@@ -476,9 +476,9 @@ struct SynthQuickLogicPass : public ScriptPass {
476476
run("dfflegalize" + legalizeArgs);
477477
} else if (family == "pp3") {
478478
run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x");
479-
run("techmap -map +/quicklogic/" + family + "/cells_map.v");
479+
run("techmap -map +/quicklogic_f4pga/" + family + "/cells_map.v");
480480
}
481-
std::string techMapArgs = " -map +/techmap.v -map +/quicklogic/" + family + "/ffs_map.v";
481+
std::string techMapArgs = " -map +/techmap.v -map +/quicklogic_f4pga/" + family + "/ffs_map.v";
482482
if (!noffmap) {
483483
run("techmap " + techMapArgs);
484484
}
@@ -497,14 +497,14 @@ struct SynthQuickLogicPass : public ScriptPass {
497497
} else if (family == "qlf_k4n8") {
498498
run("abc -lut 4 ");
499499
} else if (family == "pp3") {
500-
run("techmap -map +/quicklogic/" + family + "/latches_map.v");
500+
run("techmap -map +/quicklogic_f4pga/" + family + "/latches_map.v");
501501
if (abc9) {
502-
run("read_verilog -lib -specify -icells +/quicklogic/" + family + "/abc9_model.v");
503-
run("techmap -map +/quicklogic/" + family + "/abc9_map.v");
502+
run("read_verilog -lib -specify -icells +/quicklogic_f4pga/" + family + "/abc9_model.v");
503+
run("techmap -map +/quicklogic_f4pga/" + family + "/abc9_map.v");
504504
run("abc9 -maxlut 4 -dff");
505-
run("techmap -map +/quicklogic/" + family + "/abc9_unmap.v");
505+
run("techmap -map +/quicklogic_f4pga/" + family + "/abc9_unmap.v");
506506
} else {
507-
std::string lutDefs = "+/quicklogic/" + family + "/lutdefs.txt";
507+
std::string lutDefs = "+/quicklogic_f4pga/" + family + "/lutdefs.txt";
508508
rewrite_filename(lutDefs);
509509

510510
std::string abcArgs = "+read_lut," + lutDefs +
@@ -523,7 +523,7 @@ struct SynthQuickLogicPass : public ScriptPass {
523523

524524
if (check_label("map_cells") && (family == "qlf_k6n10" || family == "pp3")) {
525525
std::string techMapArgs;
526-
techMapArgs = "-map +/quicklogic/" + family + "/lut_map.v";
526+
techMapArgs = "-map +/quicklogic_f4pga/" + family + "/lut_map.v";
527527
run("techmap " + techMapArgs);
528528
run("clean");
529529
}

‎ql-qlf-plugin/tests/consts/consts.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ yosys -import ;# ingest plugin commands
44

55
read_verilog $::env(DESIGN_TOP).v
66

7-
synth_quicklogic -top my_top -family pp3
7+
synth_quicklogic_f4pga -top my_top -family pp3
88
stat
99
yosys cd my_top
1010
select -assert-count 1 t:my_lut

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