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Merge pull request #363 from antmicro/pcza/ql-qlf-k6n10f-dsp-extend
ql-qlf: k6n10f: Add QL_DSP3 DSP flavor
2 parents 8aa193b + 23fa345 commit 9d3f0b6

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-1443
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30 files changed

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‎ql-qlf-plugin/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,7 @@ VERILOG_MODULES = $(COMMON)/cells_sim.v \
5151
$(QLF_K6N10F_DIR)/brams_final_map.v \
5252
$(QLF_K6N10F_DIR)/brams.txt \
5353
$(QLF_K6N10F_DIR)/cells_sim.v \
54+
$(QLF_K6N10F_DIR)/dsp_sim.v \
5455
$(QLF_K6N10F_DIR)/sram1024x18.v \
5556
$(QLF_K6N10F_DIR)/TDP18K_FIFO.v \
5657
$(QLF_K6N10F_DIR)/ufifo_ctl.v \

‎ql-qlf-plugin/ql-dsp-io-regs.cc‎

Lines changed: 58 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -4,34 +4,57 @@
44
USING_YOSYS_NAMESPACE
55
PRIVATE_NAMESPACE_BEGIN
66

7+
#define MODE_BITS_REGISTER_INPUTS_ID 92
8+
#define MODE_BITS_OUTPUT_SELECT_START_ID 81
9+
#define MODE_BITS_OUTPUT_SELECT_WIDTH 3
10+
711
// ============================================================================
812

9-
const std::vector<std::string> ports2del_mult = {"feedback", "load_acc", "saturate_enable", "shift_right", "round", "subtract", "acc_fir", "dly_b"};
10-
const std::vector<std::string> ports2del_mult_add_acc = {"saturate_enable", "shift_right", "round", "acc_fir", "dly_b"};
13+
const std::vector<std::string> ports2del_mult = {"load_acc", "subtract", "acc_fir", "dly_b"};
14+
const std::vector<std::string> ports2del_mult_acc = {"acc_fir", "dly_b"};
15+
const std::vector<std::string> ports2del_mult_add = {"dly_b"};
16+
const std::vector<std::string> ports2del_extension = {"saturate_enable", "shift_right", "round"};
1117

1218
void ql_dsp_io_regs_pass(RTLIL::Module *module)
1319
{
1420

1521
for (auto cell : module->cells_) {
1622
std::string cell_type = cell.second->type.str();
17-
if (cell_type == RTLIL::escape_id("QL_DSP2")) {
23+
if (cell_type == RTLIL::escape_id("QL_DSP2") || cell_type == RTLIL::escape_id("QL_DSP3")) {
1824
auto dsp = cell.second;
1925
bool del_clk = false;
26+
bool use_dsp_cfg_params = cell_type == RTLIL::escape_id("QL_DSP3");
27+
28+
int reg_in_i;
29+
int out_sel_i;
2030

2131
// Get DSP configuration
22-
const RTLIL::SigSpec *register_inputs;
23-
register_inputs = &dsp->getPort(RTLIL::escape_id("register_inputs"));
24-
if (!register_inputs)
25-
log_error("register_inputs port not found!");
26-
auto reg_in_c = register_inputs->as_const();
27-
int reg_in_i = reg_in_c.as_int();
28-
29-
const RTLIL::SigSpec *output_select;
30-
output_select = &dsp->getPort(RTLIL::escape_id("output_select"));
31-
if (!output_select)
32-
log_error("output_select port not found!");
33-
auto out_sel_c = output_select->as_const();
34-
int out_sel_i = out_sel_c.as_int();
32+
if (use_dsp_cfg_params) {
33+
// Read MODE_BITS at correct indexes
34+
auto mode_bits = &dsp->getParam(RTLIL::escape_id("MODE_BITS"));
35+
RTLIL::Const register_inputs;
36+
register_inputs = mode_bits->bits.at(MODE_BITS_REGISTER_INPUTS_ID);
37+
reg_in_i = register_inputs.as_int();
38+
39+
RTLIL::Const output_select;
40+
output_select = mode_bits->extract(MODE_BITS_OUTPUT_SELECT_START_ID, MODE_BITS_OUTPUT_SELECT_WIDTH);
41+
out_sel_i = output_select.as_int();
42+
} else {
43+
// Read dedicated configuration ports
44+
const RTLIL::SigSpec *register_inputs;
45+
register_inputs = &dsp->getPort(RTLIL::escape_id("register_inputs"));
46+
if (!register_inputs)
47+
log_error("register_inputs port not found!");
48+
auto reg_in_c = register_inputs->as_const();
49+
reg_in_i = reg_in_c.as_int();
50+
51+
const RTLIL::SigSpec *output_select;
52+
output_select = &dsp->getPort(RTLIL::escape_id("output_select"));
53+
if (!output_select)
54+
log_error("output_select port not found!");
55+
auto out_sel_c = output_select->as_const();
56+
out_sel_i = out_sel_c.as_int();
57+
}
3558

3659
// Build new type name
3760
std::string new_type = cell_type;
@@ -73,10 +96,26 @@ void ql_dsp_io_regs_pass(RTLIL::Module *module)
7396
if (del_clk)
7497
ports2del.push_back("clk");
7598

76-
if (out_sel_i == 0 || out_sel_i == 4) {
99+
switch (out_sel_i) {
100+
case 0:
101+
case 4:
77102
ports2del.insert(ports2del.end(), ports2del_mult.begin(), ports2del_mult.end());
78-
} else {
79-
ports2del.insert(ports2del.end(), ports2del_mult_add_acc.begin(), ports2del_mult_add_acc.end());
103+
// Mark for deleton additional configuration ports
104+
if (!use_dsp_cfg_params) {
105+
ports2del.insert(ports2del.end(), ports2del_extension.begin(), ports2del_extension.end());
106+
}
107+
108+
break;
109+
case 1:
110+
case 5:
111+
ports2del.insert(ports2del.end(), ports2del_mult_acc.begin(), ports2del_mult_acc.end());
112+
break;
113+
case 2:
114+
case 3:
115+
case 6:
116+
case 7:
117+
ports2del.insert(ports2del.end(), ports2del_mult_add.begin(), ports2del_mult_add.end());
118+
break;
80119
}
81120

82121
for (auto portname : ports2del) {

‎ql-qlf-plugin/ql-dsp-macc.cc‎

Lines changed: 46 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,9 @@ PRIVATE_NAMESPACE_BEGIN
88

99
// ============================================================================
1010

11-
void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
11+
bool use_dsp_cfg_params;
12+
13+
static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
1214
{
1315
auto &st = pm.st_ql_dsp_macc;
1416

@@ -78,16 +80,21 @@ void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
7880
size_t tgt_b_width;
7981
size_t tgt_z_width;
8082

83+
string cell_base_name = "dsp_t1";
84+
string cell_size_name = "";
85+
string cell_cfg_name = "";
86+
string cell_full_name = "";
87+
8188
if (min_width <= 2 && max_width <= 2 && z_width <= 4) {
8289
// Too narrow
8390
return;
8491
} else if (min_width <= 9 && max_width <= 10 && z_width <= 19) {
85-
type = RTLIL::escape_id("dsp_t1_10x9x32");
92+
cell_size_name = "_10x9x32";
8693
tgt_a_width = 10;
8794
tgt_b_width = 9;
8895
tgt_z_width = 19;
8996
} else if (min_width <= 18 && max_width <= 20 && z_width <= 38) {
90-
type = RTLIL::escape_id("dsp_t1_20x18x64");
97+
cell_size_name = "_20x18x64";
9198
tgt_a_width = 20;
9299
tgt_b_width = 18;
93100
tgt_z_width = 38;
@@ -96,6 +103,14 @@ void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
96103
return;
97104
}
98105

106+
if (use_dsp_cfg_params)
107+
cell_cfg_name = "_cfg_params";
108+
else
109+
cell_cfg_name = "_cfg_ports";
110+
111+
cell_full_name = cell_base_name + cell_size_name + cell_cfg_name;
112+
113+
type = RTLIL::escape_id(cell_full_name);
99114
log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, RTLIL::unescape_id(type).c_str());
100115

101116
for (auto cell : {st.mul, st.add, st.mux, st.ff}) {
@@ -199,19 +214,26 @@ void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
199214
cell->setPort(RTLIL::escape_id("unsigned_a_i"), RTLIL::SigSpec(a_signed ? RTLIL::S0 : RTLIL::S1));
200215
cell->setPort(RTLIL::escape_id("unsigned_b_i"), RTLIL::SigSpec(b_signed ? RTLIL::S0 : RTLIL::S1));
201216

202-
// Connect config ports
203-
cell->setPort(RTLIL::escape_id("saturate_enable_i"), RTLIL::SigSpec(RTLIL::S0));
204-
cell->setPort(RTLIL::escape_id("shift_right_i"), RTLIL::SigSpec(RTLIL::S0, 6));
205-
cell->setPort(RTLIL::escape_id("round_i"), RTLIL::SigSpec(RTLIL::S0));
206-
cell->setPort(RTLIL::escape_id("register_inputs_i"), RTLIL::SigSpec(RTLIL::S0));
217+
// Connect config bits
218+
if (use_dsp_cfg_params) {
219+
cell->setParam(RTLIL::escape_id("SATURATE_ENABLE"), RTLIL::Const(RTLIL::S0));
220+
cell->setParam(RTLIL::escape_id("SHIFT_RIGHT"), RTLIL::Const(RTLIL::S0, 6));
221+
cell->setParam(RTLIL::escape_id("ROUND"), RTLIL::Const(RTLIL::S0));
222+
cell->setParam(RTLIL::escape_id("REGISTER_INPUTS"), RTLIL::Const(RTLIL::S0));
223+
// 3 - output post acc; 1 - output pre acc
224+
cell->setParam(RTLIL::escape_id("OUTPUT_SELECT"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3));
225+
} else {
226+
cell->setPort(RTLIL::escape_id("saturate_enable_i"), RTLIL::SigSpec(RTLIL::S0));
227+
cell->setPort(RTLIL::escape_id("shift_right_i"), RTLIL::SigSpec(RTLIL::S0, 6));
228+
cell->setPort(RTLIL::escape_id("round_i"), RTLIL::SigSpec(RTLIL::S0));
229+
cell->setPort(RTLIL::escape_id("register_inputs_i"), RTLIL::SigSpec(RTLIL::S0));
230+
// 3 - output post acc; 1 - output pre acc
231+
cell->setPort(RTLIL::escape_id("output_select_i"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3));
232+
}
207233

208234
bool subtract = (st.add->type == RTLIL::escape_id("$sub"));
209235
cell->setPort(RTLIL::escape_id("subtract_i"), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0));
210236

211-
// 3 - output post acc
212-
// 1 - output pre acc
213-
cell->setPort(RTLIL::escape_id("output_select_i"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3));
214-
215237
// Mark the cells for removal
216238
pm.autoremove(st.mul);
217239
pm.autoremove(st.add);
@@ -230,14 +252,25 @@ struct QlDspMacc : public Pass {
230252
log("\n");
231253
log(" ql_dsp_macc [options] [selection]\n");
232254
log("\n");
255+
log(" -use_dsp_cfg_params\n");
256+
log(" By default use DSP blocks with configuration bits available at module ports.\n");
257+
log(" Specifying this forces usage of DSP block with configuration bits available as module parameters\n");
258+
log("\n");
233259
}
234260

261+
void clear_flags() override { use_dsp_cfg_params = false; }
262+
235263
void execute(std::vector<std::string> a_Args, RTLIL::Design *a_Design) override
236264
{
237265
log_header(a_Design, "Executing QL_DSP_MACC pass.\n");
238266

239267
size_t argidx;
240268
for (argidx = 1; argidx < a_Args.size(); argidx++) {
269+
if (a_Args[argidx] == "-use_dsp_cfg_params") {
270+
use_dsp_cfg_params = true;
271+
continue;
272+
}
273+
241274
break;
242275
}
243276
extra_args(a_Args, argidx, a_Design);
@@ -246,6 +279,7 @@ struct QlDspMacc : public Pass {
246279
ql_dsp_macc_pm(module, module->selected_cells()).run_ql_dsp_macc(create_ql_macc_dsp);
247280
}
248281
}
282+
249283
} QlDspMacc;
250284

251285
PRIVATE_NAMESPACE_END

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