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robertszczepanskirobertszczepanski
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Update QL_DSP3 logic accordingly to QL_DSP2
Signed-off-by: Robert Szczepanski <[email protected]>
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‎ql-qlf-plugin/qlf_k6n10f/dsp_sim.v‎

Lines changed: 38 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1092,7 +1092,7 @@ module dsp_t1_sim_cfg_ports # (
10921092
wire rnd = register_inputs_i ? r_rnd : round_i;
10931093

10941094
wire sat_d1 = register_inputs_i ? r_sat_d1 : saturate_enable_i;
1095-
wire sat_d2 = output_select_i[1] ? r_sat_d1 : r_sat_d2;
1095+
wire sat_d2 = output_select_i[1] ? r_sat_d1 : r_sat_d2;
10961096

10971097
wire rnd_d1 = register_inputs_i ? r_rnd_d1 : round_i;
10981098
wire rnd_d2 = output_select_i[1] ? rnd_d1 : r_rnd_d2;
@@ -2263,6 +2263,10 @@ module dsp_t1_sim_cfg_params # (
22632263
reg r_sat;
22642264
reg r_rnd;
22652265
reg [NBITS_ACC-1:0] acc;
2266+
reg r_sat_d1;
2267+
reg r_sat_d2;
2268+
reg r_rnd_d1;
2269+
reg r_rnd_d2;
22662270

22672271
initial begin
22682272
r_a <= 0;
@@ -2326,8 +2330,14 @@ module dsp_t1_sim_cfg_params # (
23262330
wire [2:0] feedback = REGISTER_INPUTS ? r_feedback : feedback_i;
23272331
wire load_acc = REGISTER_INPUTS ? r_load_acc : load_acc_i;
23282332
wire subtract = REGISTER_INPUTS ? r_subtract : subtract_i;
2329-
wire sat = REGISTER_INPUTS ? r_sat : SATURATE_ENABLE;
2330-
wire rnd = REGISTER_INPUTS ? r_rnd : ROUND;
2333+
wire sat = REGISTER_INPUTS ? r_sat : SATURATE_ENABLE;
2334+
wire rnd = REGISTER_INPUTS ? r_rnd : ROUND;
2335+
2336+
wire sat_d1 = REGISTER_INPUTS ? r_sat_d1 : SATURATE_ENABLE;
2337+
wire sat_d2 = OUTPUT_SELECT[1] ? r_sat_d1 : r_sat_d2;
2338+
2339+
wire rnd_d1 = REGISTER_INPUTS ? r_rnd_d1 : ROUND;
2340+
wire rnd_d2 = OUTPUT_SELECT[1] ? rnd_d1 : r_rnd_d2;
23312341

23322342
// Shift right control
23332343
wire [5:0] shift_d1 = REGISTER_INPUTS ? r_shift_d1 : SHIFT_RIGHT;
@@ -2364,12 +2374,14 @@ module dsp_t1_sim_cfg_params # (
23642374
{{(NBITS_ACC-NBITS_A-NBITS_B){mult[NBITS_A+NBITS_B-1]}}, mult[NBITS_A+NBITS_B-1:0]};
23652375

23662376
// Adder
2367-
wire [NBITS_ACC-1:0] acc_fir_int = unsigned_a ? {{(NBITS_ACC-NBITS_A){1'b0}}, a} :
2377+
wire [NBITS_ACC-1:0] acc_fir_int = unsigned_a ? {{(NBITS_ACC-NBITS_A){1'b0}}, a} :
23682378
{{(NBITS_ACC-NBITS_A){a[NBITS_A-1]}}, a} ;
23692379

23702380
wire [NBITS_ACC-1:0] add_a = (subtract) ? (~mult_xtnd + 1) : mult_xtnd;
2371-
wire [NBITS_ACC-1:0] add_b = (feedback_i == 3'h0) ? acc :
2372-
(feedback_i == 3'h1) ? {{NBITS_ACC}{1'b0}} : (acc_fir_int << acc_fir);
2381+
wire [NBITS_ACC-1:0] add_b = (feedback == 3'h0) ? acc :
2382+
(feedback == 3'h1) ? {{NBITS_ACC}{1'b0}} :
2383+
(acc_fir < 6'd44 ? acc_fir_int << acc_fir :
2384+
acc_fir_int << 6'd44);
23732385

23742386
wire [NBITS_ACC-1:0] add_o = add_a + add_b;
23752387

@@ -2389,47 +2401,47 @@ module dsp_t1_sim_cfg_params # (
23892401
wire [NBITS_ACC-1:0] acc_out = (OUTPUT_SELECT[1]) ? add_o : acc;
23902402

23912403
// Round, shift, saturate
2392-
wire [NBITS_ACC-1:0] acc_rnd = (rnd && (SHIFT_RIGHT != 0)) ? (acc_out + ({{(NBITS_ACC-1){1'b0}}, 1'b1} << (SHIFT_RIGHT - 1))) :
2404+
wire [NBITS_ACC-1:0] acc_rnd = (rnd_d2 && (shift_d2 != 0)) ? (acc_out + ({{(NBITS_ACC-1){1'b0}}, 1'b1} << (shift_d2 - 1))) :
23932405
acc_out;
23942406

2395-
wire [NBITS_ACC-1:0] acc_shr = (unsigned_mode) ? (acc_rnd >> SHIFT_RIGHT) :
2396-
(acc_rnd >>> SHIFT_RIGHT);
2407+
wire [NBITS_ACC-1:0] acc_shr = acc_rnd >>> shift_d2;
23972408

2398-
wire [NBITS_ACC-1:0] acc_sat_u = (acc_shr[NBITS_ACC-1:NBITS_Z] != 0) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{NBITS_Z{1'b1}}} :
2399-
{{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}};
2409+
wire [NBITS_ACC-1:0] acc_sat_u = (&acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b1) ? {NBITS_ACC{1'b0}} :
2410+
(|acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b0 ? {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}}:
2411+
{{(NBITS_ACC-NBITS_Z){1'b0}},{NBITS_Z{1'b1}}});
24002412

24012413
wire [NBITS_ACC-1:0] acc_sat_s = ((|acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b0) ||
24022414
(&acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b1)) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}} :
24032415
{{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_ACC-1],{NBITS_Z-1{~acc_shr[NBITS_ACC-1]}}}};
24042416

2405-
wire [NBITS_ACC-1:0] acc_sat = (sat) ? ((unsigned_mode) ? acc_sat_u : acc_sat_s) : acc_shr;
2417+
wire [NBITS_ACC-1:0] acc_sat = sat_d2 ? (unsigned_mode ? acc_sat_u : acc_sat_s) : acc_shr;
24062418

24072419
// Output signals
2408-
wire [NBITS_Z-1:0] z0;
2409-
reg [NBITS_Z-1:0] z1;
2410-
wire [NBITS_Z-1:0] z2;
2420+
wire [NBITS_ACC-1:0] z0;
2421+
reg [NBITS_ACC-1:0] z1;
2422+
wire [NBITS_ACC-1:0] z2;
24112423

2412-
assign z0 = mult_xtnd[NBITS_Z-1:0];
2413-
assign z2 = acc_sat[NBITS_Z-1:0];
2424+
assign z0 = unsigned_mode ? mult_xtnd >> shift_d2 : mult_xtnd >>> shift_d2;
2425+
assign z2 = acc_sat;
24142426

24152427
initial z1 <= 0;
24162428

24172429
always @(posedge clock_i or posedge s_reset)
24182430
if (s_reset)
24192431
z1 <= 0;
24202432
else begin
2421-
z1 <= (OUTPUT_SELECT == 3'b100) ? z0 : z2;
2433+
z1 <= (OUTPUT_SELECT == 3'b100) ? mult_xtnd : z2;
24222434
end
24232435

24242436
// Output mux
2425-
assign z_o = (OUTPUT_SELECT == 3'h0) ? z0 :
2426-
(OUTPUT_SELECT == 3'h1) ? z2 :
2427-
(OUTPUT_SELECT == 3'h2) ? z2 :
2428-
(OUTPUT_SELECT == 3'h3) ? z2 :
2429-
(OUTPUT_SELECT == 3'h4) ? z1 :
2430-
(OUTPUT_SELECT == 3'h5) ? z1 :
2431-
(OUTPUT_SELECT == 3'h6) ? z1 :
2432-
z1; // if OUTPUT_SELECT == 3'h7
2437+
assign z_o = (OUTPUT_SELECT == 3'h0) ? mult_xtnd[NBITS_Z-1:0] :
2438+
(OUTPUT_SELECT == 3'h1) ? z2[NBITS_Z-1:0] :
2439+
(OUTPUT_SELECT == 3'h2) ? z2[NBITS_Z-1:0] :
2440+
(OUTPUT_SELECT == 3'h3) ? z2[NBITS_Z-1:0] :
2441+
(OUTPUT_SELECT == 3'h4) ? z1[NBITS_Z-1:0] :
2442+
(OUTPUT_SELECT == 3'h5) ? z1[NBITS_Z-1:0] :
2443+
(OUTPUT_SELECT == 3'h6) ? z1[NBITS_Z-1:0] :
2444+
z1[NBITS_Z-1:0]; // if OUTPUT_SELECT == 3'h7
24332445

24342446
// B input delayed passthrough
24352447
initial dly_b_o <= 0;

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