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lines changed Original file line number Diff line number Diff line change @@ -1925,6 +1925,13 @@ void UhdmAst::process_begin()
19251925 }
19261926 }
19271927 });
1928+ // TODO: find out how to set VERILOG_FRONTEND::sv_mode to true
1929+ // simplify checks if sv_mode is set to ture when wire is declared inside unnamed block
1930+ /* visit_one_to_many({vpiVariables}, obj_h, [&](AST::AstNode *node) {
1931+ if (node) {
1932+ current_node->children.push_back(node);
1933+ }
1934+ });*/
19281935}
19291936
19301937void UhdmAst::process_operation ()
@@ -2722,6 +2729,12 @@ void UhdmAst::process_sys_func_call()
27222729 current_node->children .push_back (node);
27232730 }
27242731 });
2732+
2733+ // skip $value$plusargs function, as it is simulation function
2734+ if (current_node->str == " \\ $value$plusargs" ) {
2735+ delete current_node;
2736+ current_node = nullptr ;
2737+ }
27252738}
27262739
27272740void UhdmAst::process_func_call ()
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