Skip to content

Commit d149693

Browse files
mkurc-antmkurc-ant
authored
Merge pull request #361 from antmicro/k6n10f-readd-dffs
Added back regular D flip-flops and latches for k6n10f
2 parents 6bc9630 + 36ac139 commit d149693

File tree

3 files changed

+273
-3
lines changed

3 files changed

+273
-3
lines changed

‎ql-qlf-plugin/qlf_k6n10f/cells_sim.v‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -124,6 +124,33 @@ module frac_lut6(
124124

125125
endmodule
126126

127+
(* abc9_flop, lib_whitebox *)
128+
module dff(
129+
output reg Q,
130+
input wire D,
131+
(* clkbuf_sink *)
132+
input wire C
133+
);
134+
initial Q <= 1'b0;
135+
136+
always @(posedge C)
137+
Q <= D;
138+
139+
endmodule
140+
141+
(* abc9_flop, lib_whitebox *)
142+
module dffn(
143+
output reg Q,
144+
input wire D,
145+
(* clkbuf_sink *)
146+
input wire C
147+
);
148+
initial Q <= 1'b0;
149+
150+
always @(negedge C)
151+
Q <= D;
152+
153+
endmodule
127154

128155
(* abc9_flop, lib_whitebox *)
129156
module dffsre(

‎ql-qlf-plugin/synth_quicklogic.cc‎

Lines changed: 25 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,11 @@ struct SynthQuickLogicPass : public ScriptPass {
8484
log(" -no_ff_map\n");
8585
log(" By default ff techmap is turned on. Specifying this switch turns it off.\n");
8686
log("\n");
87+
log(" -nosdff\n");
88+
log(" By default infer synchronous S/R flip-flops for architectures\n");
89+
log(" that support them. \n");
90+
log(" Specifying this switch turns it off.\n");
91+
log("\n");
8792
log("\n");
8893
log("The following commands are executed by this synthesis command:\n");
8994
help_script();
@@ -97,6 +102,7 @@ struct SynthQuickLogicPass : public ScriptPass {
97102
bool abcOpt;
98103
bool abc9;
99104
bool noffmap;
105+
bool nosdff;
100106

101107
void clear_flags() override
102108
{
@@ -112,6 +118,7 @@ struct SynthQuickLogicPass : public ScriptPass {
112118
abc9 = true;
113119
noffmap = false;
114120
nodsp = false;
121+
nosdff = false;
115122
}
116123

117124
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -177,6 +184,10 @@ struct SynthQuickLogicPass : public ScriptPass {
177184
noffmap = true;
178185
continue;
179186
}
187+
if (args[argidx] == "-nosdff") {
188+
nosdff = true;
189+
continue;
190+
}
180191

181192
break;
182193
}
@@ -192,6 +203,10 @@ struct SynthQuickLogicPass : public ScriptPass {
192203
abc9 = false;
193204
}
194205

206+
if (family == "qlf_k4n8") {
207+
nosdff = true;
208+
}
209+
195210
if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) {
196211
log_warning("delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.\n");
197212
design->scratchpad_set_int("abc9.D", 41667); // 12MHz = 83.33.. ns; divided by two to allow for interconnect delay.
@@ -230,9 +245,13 @@ struct SynthQuickLogicPass : public ScriptPass {
230245
}
231246

232247
std::string noDFFArgs;
248+
if (nosdff) {
249+
noDFFArgs += " -nosdff";
250+
}
233251
if (family == "qlf_k4n8") {
234-
noDFFArgs = " -nodffe -nosdff";
252+
noDFFArgs += " -nodffe";
235253
}
254+
236255
if (check_label("coarse")) {
237256
run("check");
238257
run("opt -nodffe -nosdff");
@@ -366,7 +385,11 @@ struct SynthQuickLogicPass : public ScriptPass {
366385
// FIXME: dfflegalize seems to leave $_DLATCH_[NP]_ even if it
367386
// is not allowed. So we allow them and map them later to
368387
// $_DLATCHSR_[NP]NN_.
369-
run("dfflegalize -cell $_DFFSRE_?NNP_ 0 -cell $_SDFFE_?N?P_ 0 -cell $_DLATCHSR_?NN_ 0 -cell $_DLATCH_?_ 0");
388+
std::string legalizeArgs = " -cell $_DFFSRE_?NNP_ 0 -cell $_DLATCHSR_?NN_ 0 -cell $_DLATCH_?_ 0";
389+
if (!nosdff) {
390+
legalizeArgs += " -cell $_SDFFE_?N?P_ 0";
391+
}
392+
run("dfflegalize" + legalizeArgs);
370393
} else if (family == "pp3") {
371394
run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x");
372395
run("techmap -map +/quicklogic/" + family + "/cells_map.v");

‎ql-qlf-plugin/tests/dffs/dffs.tcl‎

Lines changed: 221 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -412,7 +412,7 @@ select -assert-count 3 t:\$lut
412412
design -reset
413413

414414
# =============================================================================
415-
# qlf_k6n10f
415+
# qlf_k6n10f (with synchronous S/R flip-flops)
416416

417417
read_verilog $::env(DESIGN_TOP).v
418418
design -save read
@@ -716,6 +716,226 @@ select -assert-count 1 t:latchnsre
716716
#select -assert-count 1 t:\$lut
717717

718718

719+
design -reset
720+
721+
# =============================================================================
722+
# qlf_k6n10f (no synchronous S/R flip-flops)
723+
724+
read_verilog $::env(DESIGN_TOP).v
725+
design -save read
726+
727+
# DFF
728+
hierarchy -top my_dff
729+
yosys proc
730+
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dff -nosdff
731+
design -load postopt
732+
yosys cd my_dff
733+
stat
734+
select -assert-count 1 t:dffsre
735+
736+
# DFFN
737+
design -load read
738+
hierarchy -top my_dffn
739+
yosys proc
740+
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffn -nosdff
741+
design -load postopt
742+
yosys cd my_dffn
743+
stat
744+
select -assert-count 1 t:dffnsre
745+
746+
747+
# DFFSRE from DFFR_N
748+
design -load read
749+
hierarchy -top my_dffr_n
750+
yosys proc
751+
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffr_n -nosdff
752+
design -load postopt
753+
yosys cd my_dffr_n
754+
stat
755+
select -assert-count 1 t:dffsre
756+
757+
# DFFSRE from DFFR_P
758+
design -load read
759+
hierarchy -top my_dffr_p
760+
yosys proc
761+
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffr_p -nosdff
762+
design -load postopt
763+
yosys cd my_dffr_p
764+
stat
765+
select -assert-count 1 t:dffsre
766+
select -assert-count 1 t:\$lut
767+
768+
# DFFSRE from DFFRE_N
769+
design -load read
770+
hierarchy -top my_dffre_n
771+
yosys proc
772+
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffre_n -nosdff
773+
design -load postopt
774+
yosys cd my_dffre_n
775+
stat
776+
select -assert-count 1 t:dffsre
777+
778+
# DFFSRE from DFFRE_P
779+
design -load read
780+
hierarchy -top my_dffre_p
781+
yosys proc
782+
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffre_p -nosdff
783+
design -load postopt
784+
yosys cd my_dffre_p
785+
stat
786+
select -assert-count 1 t:dffsre
787+
select -assert-count 1 t:\$lut
788+
789+
790+
# DFFSRE from DFFS_N
791+
design -load read
792+
hierarchy -top my_dffs_n
793+
yosys proc
794+
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffs_n -nosdff
795+
design -load postopt
796+
yosys cd my_dffs_n
797+
stat
798+
select -assert-count 1 t:dffsre
799+
800+
# DFFSRE from DFFS_P
801+
design -load read
802+
hierarchy -top my_dffs_p
803+
yosys proc
804+
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffs_p -nosdff
805+
design -load postopt
806+
yosys cd my_dffs_p
807+
stat
808+
select -assert-count 1 t:dffsre
809+
select -assert-count 1 t:\$lut
810+
811+
# DFFSRE from DFFSE_N
812+
design -load read
813+
hierarchy -top my_dffse_n
814+
yosys proc
815+
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffse_n -nosdff
816+
design -load postopt
817+
yosys cd my_dffse_n
818+
stat
819+
select -assert-count 1 t:dffsre
820+
821+
# DFFSRE from DFFSE_P
822+
design -load read
823+
hierarchy -top my_dffse_p
824+
yosys proc
825+
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffse_p -nosdff
826+
design -load postopt
827+
yosys cd my_dffse_p
828+
stat
829+
select -assert-count 1 t:dffsre
830+
select -assert-count 1 t:\$lut
831+
832+
833+
# LATCH
834+
design -load read
835+
hierarchy -top my_latch
836+
yosys proc
837+
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latch -nosdff
838+
design -load postopt
839+
yosys cd my_latch
840+
stat
841+
select -assert-count 1 t:latchsre
842+
843+
# LATCHN
844+
design -load read
845+
hierarchy -top my_latchn
846+
yosys proc
847+
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchn -nosdff
848+
design -load postopt
849+
yosys cd my_latchn
850+
stat
851+
select -assert-count 1 t:latchnsre
852+
853+
854+
## LATCHSRE from LATCHR_N
855+
#design -load read
856+
#hierarchy -top my_latchr_n
857+
#yosys proc
858+
#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchr_n -nosdff
859+
#design -load postopt
860+
#yosys cd my_latchr_n
861+
#stat
862+
#select -assert-count 1 t:latchr_n
863+
#
864+
## LATCHSRE from LATCHR_P
865+
#design -load read
866+
#hierarchy -top my_latchr_p
867+
#yosys proc
868+
#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchr_p -nosdff
869+
#design -load postopt
870+
#yosys cd my_latchr_p
871+
#stat
872+
#select -assert-count 1 t:latchr_p
873+
#select -assert-count 1 t:\$lut
874+
#
875+
## LATCHSRE from LATCHS_N
876+
#design -load read
877+
#hierarchy -top my_latchs_n
878+
#yosys proc
879+
#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchs_n -nosdff
880+
#design -load postopt
881+
#yosys cd my_latchs_n
882+
#stat
883+
#select -assert-count 1 t:latchs_n
884+
#
885+
## LATCHSRE from LATCHS_P
886+
#design -load read
887+
#hierarchy -top my_latchs_p
888+
#yosys proc
889+
#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchs_p -nosdff
890+
#design -load postopt
891+
#yosys cd my_latchs_p
892+
#stat
893+
#select -assert-count 1 t:latchs_p
894+
#select -assert-count 1 t:\$lut
895+
#
896+
#
897+
## LATCHSRE from LATCHNR_N
898+
#design -load read
899+
#hierarchy -top my_latchnr_n
900+
#yosys proc
901+
#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchnr_n -nosdff
902+
#design -load postopt
903+
#yosys cd my_latchnr_n
904+
#stat
905+
#select -assert-count 1 t:latchnr_n
906+
#
907+
## LATCHSRE from LATCHNR_P
908+
#design -load read
909+
#hierarchy -top my_latchnr_p
910+
#yosys proc
911+
#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchnr_p -nosdff
912+
#design -load postopt
913+
#yosys cd my_latchnr_p
914+
#stat
915+
#select -assert-count 1 t:latchnr_p
916+
#select -assert-count 1 t:\$lut
917+
#
918+
## LATCHSRE from LATCHNS_N
919+
#design -load read
920+
#hierarchy -top my_latchns_n
921+
#yosys proc
922+
#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchns_n -nosdff
923+
#design -load postopt
924+
#yosys cd my_latchns_n
925+
#stat
926+
#select -assert-count 1 t:latchns_n
927+
#
928+
## LATCHSRE from LATCHNS_P
929+
#design -load read
930+
#hierarchy -top my_latchns_p
931+
#yosys proc
932+
#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchns_p -nosdff
933+
#design -load postopt
934+
#yosys cd my_latchns_p
935+
#stat
936+
#select -assert-count 1 t:latchns_p
937+
#select -assert-count 1 t:\$lut
938+
719939
design -reset
720940

721941
# =============================================================================

0 commit comments

Comments
 (0)