@@ -2044,9 +2044,18 @@ void UhdmAst::process_initial()
20442044 });
20452045}
20462046
2047- void UhdmAst::process_begin ()
2047+ void UhdmAst::process_begin (bool is_named )
20482048{
20492049 current_node = make_ast_node (AST::AST_BLOCK);
2050+ // TODO: find out how to set VERILOG_FRONTEND::sv_mode to true
2051+ // simplify checks if sv_mode is set to ture when wire is declared inside unnamed block
2052+ if (is_named) {
2053+ visit_one_to_many ({vpiVariables}, obj_h, [&](AST::AstNode *node) {
2054+ if (node) {
2055+ current_node->children .push_back (node);
2056+ }
2057+ });
2058+ }
20502059 visit_one_to_many ({vpiStmt}, obj_h, [&](AST::AstNode *node) {
20512060 if (node) {
20522061 if ((node->type == AST::AST_ASSIGN_EQ || node->type == AST::AST_ASSIGN_LE) && node->children .size () == 1 ) {
@@ -2062,15 +2071,6 @@ void UhdmAst::process_begin()
20622071 }
20632072 }
20642073 });
2065- // TODO: find out how to set VERILOG_FRONTEND::sv_mode to true
2066- // simplify checks if sv_mode is set to ture when wire is declared inside unnamed block
2067- if (!current_node->str .empty ()) {
2068- visit_one_to_many ({vpiVariables}, obj_h, [&](AST::AstNode *node) {
2069- if (node) {
2070- current_node->children .push_back (node);
2071- }
2072- });
2073- }
20742074}
20752075
20762076void UhdmAst::process_operation ()
@@ -3505,10 +3505,10 @@ AST::AstNode *UhdmAst::process_object(vpiHandle obj_handle)
35053505 process_initial ();
35063506 break ;
35073507 case vpiNamedBegin:
3508- process_begin ();
3508+ process_begin (true );
35093509 break ;
35103510 case vpiBegin:
3511- process_begin ();
3511+ process_begin (false );
35123512 // for unnamed block, reset block name
35133513 current_node->str = " " ;
35143514 break ;
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