Updated tests

Signed-off-by: Maciej Kurc <[email protected]>

Author: mkurc-ant

ql-qlf-plugin/tests/qlf_k6n10f/dsp_madd/dsp_madd.v

@@ -23,8 +23,12 @@ module madd_simple_ports (
 
     // There is no support for autmoatic inference of multiply+add hence the
     // DSP cell needs to be instanced manually.
+    //
+    // To test the type change the "is_inferred" attribute is set here
+    // explicitily to mimic possible inference
 
     // B * coeff[C] + A
+    (* is_inferred=1 *)
     dsp_t1_10x9x32_cfg_ports # (
         .COEFF_0            (10'h011),
         .COEFF_1            (10'h022),
@@ -62,8 +66,12 @@ module madd_simple_params (
 
     // There is no support for autmoatic inference of multiply+add hence the
     // DSP cell needs to be instanced manually.
+    //
+    // To test the type change the "is_inferred" attribute is set here
+    // explicitily to mimic possible inference
 
     // B * coeff[C] + A
+    (* is_inferred=1 *)
     dsp_t1_10x9x32_cfg_params # (
         .COEFF_0            (10'h011),
         .COEFF_1            (10'h022),

ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.tcl

@@ -48,7 +48,6 @@ proc test_dsp_cfg_ports {top expected_cell_suffix cells2match} {
     design -load postopt
     yosys cd ${top}
     select -assert-count ${cells2match} t:QL_DSP2${expected_cell_suffix}
-    select -assert-count 0 t:QL_DSP2
     select -assert-count 0 t:dsp_t1_10x9x32_cfg_ports
     select -assert-count 0 t:dsp_t1_20x18x64_cfg_ports
 
@@ -71,7 +70,6 @@ proc test_dsp_cfg_params {top expected_cell_suffix cells2match} {
     design -load postopt
     yosys cd ${TOP}
     select -assert-count ${cells2match} t:QL_DSP3${expected_cell_suffix}
-    select -assert-count 0 t:QL_DSP3
     select -assert-count 0 t:dsp_t1_10x9x32_cfg_params
     select -assert-count 0 t:dsp_t1_20x18x64_cfg_params
 
@@ -87,18 +85,15 @@ proc test_dsp_cfg_params {top expected_cell_suffix cells2match} {
 #           of the inference, eg. _MULT, _MACC_REGIN, MADD_REGIN_REGOUT
 proc test_dsp_cfg_conflict {top expected_cell_suffix} {
     set TOP ${top}
-    set USE_DSP_CFG_PARAMS 1
+    set USE_DSP_CFG_PARAMS 0
     design -load read
     hierarchy -top $TOP
     check_equiv ${TOP} ${USE_DSP_CFG_PARAMS}
     design -load postopt
     yosys cd ${TOP}
-    select -assert-count 1 t:QL_DSP2${expected_cell_suffix}
-    select -assert-count 1 t:QL_DSP3${expected_cell_suffix}
-    select -assert-count 0 t:QL_DSP2
+    select -assert-count 2 t:QL_DSP2${expected_cell_suffix}
     select -assert-count 0 t:dsp_t1_10x9x32_cfg_ports
     select -assert-count 0 t:dsp_t1_20x18x64_cfg_ports
-    select -assert-count 0 t:QL_DSP3
     select -assert-count 0 t:dsp_t1_10x9x32_cfg_params
     select -assert-count 0 t:dsp_t1_20x18x64_cfg_params
 
@@ -111,12 +106,12 @@ yosys -import  ;# ingest plugin commands
 read_verilog dsp_simd.v
 design -save read
 
-test_dsp_cfg_ports      "simd_mult_explicit_ports"      "_MULT_REGIN"   1
-test_dsp_cfg_params     "simd_mult_explicit_params"     "_MULT_REGIN"   1
-test_dsp_cfg_ports      "simd_mult_inferred"            "_MULT"         1
-test_dsp_cfg_params     "simd_mult_inferred"            "_MULT"         1
-test_dsp_cfg_ports      "simd_mult_odd_ports"           "_MULT_REGIN"   2
-test_dsp_cfg_params     "simd_mult_odd_params"          "_MULT_REGIN"   2
-test_dsp_cfg_ports      "simd_mult_conflict_ports"      "_MULT_REGIN"   2
-test_dsp_cfg_conflict   "simd_mult_conflict_config"     "_MULT_REGIN"
+test_dsp_cfg_ports      "simd_mult_explicit_ports"      ""       1
+test_dsp_cfg_params     "simd_mult_explicit_params"     ""       1
+test_dsp_cfg_ports      "simd_mult_inferred"            "_MULT"  1
+test_dsp_cfg_params     "simd_mult_inferred"            "_MULT"  1
+test_dsp_cfg_ports      "simd_mult_odd_ports"           ""       2
+test_dsp_cfg_params     "simd_mult_odd_params"          ""       2
+test_dsp_cfg_ports      "simd_mult_conflict_ports"      ""       2
+test_dsp_cfg_conflict   "simd_mult_conflict_config"     ""
 

ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v

@@ -371,33 +371,32 @@ module simd_mult_conflict_config (
     output wire [15:0]  z1
 );
 
-    dsp_t1_10x9x32_cfg_params #(
-        .OUTPUT_SELECT      (3'd0),
-        .SATURATE_ENABLE    (1'b0),
-        .SHIFT_RIGHT        (6'd0),
-        .ROUND              (1'b0),
-        .REGISTER_INPUTS    (1'b1)
-    ) dsp_0 (
+    dsp_t1_10x9x32_cfg_ports dsp_0 (
         .a_i    (a0),
         .b_i    (b0),
         .z_o    (z0),
 
-        .clock_i            (clk),
+        .clock_i            (clk0),
 
         .feedback_i         (3'd0),
         .load_acc_i         (1'b0),
         .unsigned_a_i       (1'b1),
         .unsigned_b_i       (1'b1),
 
-        .subtract_i         (1'b0)
+        .output_select_i    (3'd0),
+        .saturate_enable_i  (1'b0),
+        .shift_right_i      (6'd0),
+        .round_i            (1'b0),
+        .subtract_i         (1'b0),
+        .register_inputs_i  (1'b0)
     );
 
     dsp_t1_10x9x32_cfg_ports dsp_1 (
         .a_i    (a1),
         .b_i    (b1),
         .z_o    (z1),
 
-        .clock_i            (clk),
+        .clock_i            (clk1),
 
         .feedback_i         (3'd0),
         .load_acc_i         (1'b0),
@@ -409,7 +408,7 @@ module simd_mult_conflict_config (
         .shift_right_i      (6'd0),
         .round_i            (1'b0),
         .subtract_i         (1'b0),
-        .register_inputs_i  (1'b1)
+        .register_inputs_i  (1'b0)
     );
 
 endmodule

ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd_post_synth_sim/dsp_simd_post_synth_sim.tcl

@@ -24,7 +24,7 @@ opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/simd_mult_explicit_ports_post_synth.v
-select -assert-count 1 t:QL_DSP2_MULT_REGIN
+select -assert-count 1 t:QL_DSP2
 
 select -clear
 design -load dsp_simd
@@ -35,4 +35,4 @@ opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/simd_mult_explicit_params_post_synth.v
-select -assert-count 1 t:QL_DSP3_MULT_REGIN
+select -assert-count 1 t:QL_DSP3